library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_package.all;

package dma_package is
  component dma is
    generic(
      -- Value 0 cannot stream
      -- Value 1 only slaves with async ACK can stream
      -- Value 2 only slaves with combined latency <= 2 can stream
      -- Value 3 only slaves with combined latency <= 6 can stream
      -- Value 4 only slaves with combined latency <= 14 can stream
      -- ....
      logRingLen : integer := 4
    );
    port(
      -- Common wishbone signals
      clk        : in  std_logic;
      rst        : in  std_logic;
      -- Slave control port
      slave_i    : in  wishbone_slave_in;
      slave_o    : out wishbone_slave_out;
      -- Master reader port
      r_master_i : in  wishbone_master_in;
      r_master_o : out wishbone_master_out;
      -- Master writer port
      w_master_i : in  wishbone_master_in;
      w_master_o : out wishbone_master_out;
      -- Pulsed high completion signal
      interrupt  : out std_logic
    );
  end component;
end dma_package;