library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_package.all;

package test_slave_package is
  component test_slave is
    generic(
      delay : integer := 1
    );
    port(
      -- Common wishbone signals
      clk        : in  std_logic;
      rst        : in  std_logic;
      -- Slave control port
      slave_i    : in  wishbone_slave_in;
      slave_o    : out wishbone_slave_out
    );
  end component;
end test_slave_package;