88 lines
1.6 KiB
VHDL
88 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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library ip;
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use ip.wishbone_package.all;
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entity bench_gpio is
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end entity bench_gpio;
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architecture RTL of bench_gpio is
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signal clk : std_logic;
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signal rst : std_logic;
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signal clr : std_logic;
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signal wb_in : wishbone_v3_slave_in;
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signal wb_out : wishbone_v3_slave_out;
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signal gpio : std_logic_vector(31 downto 0);
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begin
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gpio_inst : entity design.gpio
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port map(
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clk => clk,
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rst => rst,
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clr => clr,
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wb_in => wb_in,
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wb_out => wb_out,
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gpio => gpio
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);
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clock_driver : process
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constant period : time := 10 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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test : process is
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begin
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rst <= '1';
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clr <= '0';
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wb_in.STB <= '0';
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wb_in.CYC <= '0';
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wb_in.ADR <= (others => '0');
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wb_in.DAT <= (others => '0');
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wb_in.SEL <= (others => '1');
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wb_in.WE <= '0';
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wait for 20 ns;
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wait until rising_edge(clk);
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rst <= '0';
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wait until rising_edge(clk);
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wb_in.DAT <= x"0000ffff";
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wb_in.WE <= '1';
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wb_in.STB <= '1';
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wb_in.CYC <= '1';
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wait until rising_edge(clk);
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wb_in.WE <= '0';
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wb_in.STB <= '0';
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wb_in.CYC <= '0';
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wait until rising_edge(clk);
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wb_in.WE <= '1';
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wb_in.STB <= '1';
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wb_in.CYC <= '1';
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wb_in.ADR <= x"00000004";
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wb_in.DAT <= x"12345678";
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wait until rising_edge(clk);
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wb_in.WE <= '0';
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wb_in.STB <= '0';
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wb_in.CYC <= '0';
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wait until rising_edge(clk);
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wb_in.ADR <= x"00000008";
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wait;
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end process test;
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gpio(31 downto 28) <= (others => '1');
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end architecture RTL;
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