160 lines
4.2 KiB
VHDL
160 lines
4.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library design;
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use design.all;
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use design.flashrom_pkg.all;
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entity bench_flashrom_controller is
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end entity bench_flashrom_controller;
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architecture rtl of bench_flashrom_controller is
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signal clk : std_logic;
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signal rst : std_logic;
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procedure waitclk is
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begin
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wait until rising_edge(clk);
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end procedure waitclk;
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procedure waitnclk(n : integer) is
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begin
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for i in 1 to n loop
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wait until rising_edge(clk);
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end loop;
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end procedure waitnclk;
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procedure strobe(signal s : out std_logic) is
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begin
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s <= '1';
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waitclk;
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s <= '0';
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waitclk;
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end procedure strobe;
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signal clr : std_logic;
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signal ready : std_logic;
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signal page : std_logic_vector(FLASHROM_PAGE_ADDR_WIDTH - 1 downto 0);
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signal sync_stb : std_logic;
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signal load_stb : std_logic;
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signal status_update_stb : std_logic;
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signal status : std_logic_vector(7 downto 0);
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signal info : std_logic_vector(31 downto 0);
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signal data_in : std_logic_vector(7 downto 0) := x"00";
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signal data_in_next : std_logic;
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signal data_out : std_logic_vector(7 downto 0);
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signal data_out_valid : std_logic;
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signal spi_si : std_logic;
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signal spi_so : std_logic;
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signal spi_sck : std_logic;
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signal spi_reset_n : std_logic;
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signal spi_cs_n : std_logic;
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signal spi_wp_n : std_logic;
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signal spi_busy : std_logic;
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signal spi_clk_cnt : integer := 0;
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begin
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DataFlash_inst : entity work.DataFlash
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generic map(
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flashmemory => "devicemodels/memory.txt",
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Rapid_interface => true,
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fsck => 66,
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DEVICE => "AT45DB011D", --AT45DB011D
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Tsck => 13.6 ns)
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port map(
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SI => spi_si,
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CSB => spi_cs_n,
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SCK => spi_sck,
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WPB => spi_wp_n,
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RESETB => spi_reset_n,
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SO => spi_so,
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RDYBSY => spi_busy
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);
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flashrom_controller_inst : entity design.flashrom_controller
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port map(
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clk => clk,
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rst => rst,
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clr => clr,
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ready => ready,
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page => page,
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sync_stb => sync_stb,
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load_stb => load_stb,
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status_update_stb => status_update_stb,
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status => status,
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info => info,
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data_in => data_in,
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data_in_next => data_in_next,
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data_out => data_out,
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data_out_valid => data_out_valid,
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spi_si => spi_si,
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spi_so => spi_so,
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spi_sck => spi_sck,
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spi_reset_n => spi_reset_n,
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spi_cs_n => spi_cs_n,
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spi_wp_n => spi_wp_n
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);
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-- clock driver
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clock_driver : process
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constant PERIOD : time := 10 ns;
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begin
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clk <= '0';
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wait for PERIOD / 2;
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clk <= '1';
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wait for PERIOD / 2;
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end process clock_driver;
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--testbench
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bench : process is
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begin
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rst <= '1';
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clr <= '0';
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status_update_stb <= '0';
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load_stb <= '0';
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page <= (others => '0');
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wait for 10 ns * 2;
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wait until (rising_edge(clk));
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rst <= '0';
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wait for 10 ns * 2;
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wait until (rising_edge(clk));
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-- bench code here
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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wait for 100 us;
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strobe(sync_stb); -- Make sure background_op_enable is '1' in device model (power up delay)
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wait until ready = '1';
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strobe(status_update_stb);
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wait until ready = '1';
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wait until spi_busy = '1';
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wait for 100 us;
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strobe(status_update_stb);
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wait until ready = '1';
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strobe(load_stb);
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wait;
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end process bench;
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spiclkcounter : process is
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begin
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wait until data_out_valid = '1';
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spi_clk_cnt <= spi_clk_cnt + 1;
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end process spiclkcounter;
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data_provider : process is
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begin
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wait until data_in_next = '1';
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--wait until data_in_next = '1';
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data_in <= std_logic_vector(unsigned(data_in) + 1);
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end process data_provider;
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end architecture rtl;
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