mor1kx-bemicrocv/quartus/mor1kx-bemicrocv.out.sdc

## Generated SDC file "mor1kx-bemicrocv.out.sdc"

## Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, the Altera Quartus Prime License Agreement,
## the Altera MegaCore Function License Agreement, or other 
## applicable license agreement, including, without limitation, 
## that your use is for the sole purpose of programming logic 
## devices manufactured by Altera and sold by Altera or its 
## authorized distributors.  Please refer to the applicable 
## agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition"

## DATE    "Thu Jun 16 20:57:22 2016"

##
## DEVICE  "5CEFA2F23C7"
##


#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3



#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {clk_hw} -period 13.333 -waveform { 0.000 10.000 } [get_ports { clk_hw }]
create_clock -name {mem_dqs[0]_IN} -period 3.333 -waveform { 0.000 1.667 } [get_ports {mem_dqs[0]}] -add
create_clock -name {mem_dqs[1]_IN} -period 3.333 -waveform { 0.000 1.667 } [get_ports {mem_dqs[1]}] -add


#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 1000000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] 
create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 1000000 -phase 270.000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll3~PLL_OUTPUT_COUNTER|divclk}] 
create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_avl_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 5000000 -phase 9.000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] 
create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 5000000 -phase 9.000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll6_phy~PLL_OUTPUT_COUNTER|divclk}] 
create_generated_clock -name {ddr3_inst|ddr3_inst|pll0|pll_config_clk} -source [get_ports {{clk_hw}}] -multiply_by 6000000 -divide_by 15000000 -master_clock {clk_hw} [get_pins {ddr3_inst|ddr3_inst|pll0|pll7~PLL_OUTPUT_COUNTER|divclk}] 
create_generated_clock -name {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_registers {ddr3_inst|ddr3_inst|p0|umemphy|uio_pads|dq_ddio[*].ubidir_dq_dqs|altdq_dqs2_inst|dqs_enable_ctrl~DQSENABLEOUT_DFF}] 
create_generated_clock -name {mem_ck[0]} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_ck[0]}] 
create_generated_clock -name {mem_ck_n[0]} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} -invert [get_ports {mem_ck_n[0]}] 
create_generated_clock -name {mem_dqs[0]_OUT} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_dqs[0]}] -add
create_generated_clock -name {mem_dqs[1]_OUT} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_dqs[1]}] -add
create_generated_clock -name {mem_dqs_n[0]_OUT} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_dqs_n[0]}] 
create_generated_clock -name {mem_dqs_n[1]_OUT} -source [get_pins {ddr3_inst|ddr3_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -master_clock {ddr3_inst|ddr3_inst|pll0|pll_afi_clk} [get_ports {mem_dqs_n[1]}] 


#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[1]_OUT}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs_n[0]_OUT}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_OUT}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_OUT}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_ck_n[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {mem_ck[0]}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.100  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.100  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.100  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.100  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.100  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.100  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.100  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.100  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {clk_hw}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {clk_hw}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {clk_hw}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {clk_hw}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {clk_hw}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {clk_hw}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|ddr3_p0_sampling_clock}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {clk_hw}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {clk_hw}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {clk_hw}] -setup 0.100  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -rise_to [get_clocks {clk_hw}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {clk_hw}] -setup 0.100  
set_clock_uncertainty -rise_from [get_clocks {clk_hw}] -fall_to [get_clocks {clk_hw}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {clk_hw}] -setup 0.100  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -rise_to [get_clocks {clk_hw}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {clk_hw}] -setup 0.100  
set_clock_uncertainty -fall_from [get_clocks {clk_hw}] -fall_to [get_clocks {clk_hw}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280  
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280  
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -hold 0.050  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -hold 0.050  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {clk_hw}]  0.110  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {clk_hw}]  0.110  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -hold 0.060  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -setup 0.080  
set_clock_uncertainty -rise_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_ck_n[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.226  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] -hold 0.050  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -hold 0.050  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_dq_write_clk}] -hold 0.050  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {clk_hw}]  0.110  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {clk_hw}]  0.110  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -rise_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -hold 0.060  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -setup 0.080  
set_clock_uncertainty -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -fall_to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -hold 0.060  


#**************************************************************
# Set Input Delay
#**************************************************************

set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.158 [get_ports {mem_dq[0]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.296 [get_ports {mem_dq[0]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.158 [get_ports {mem_dq[1]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.296 [get_ports {mem_dq[1]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.158 [get_ports {mem_dq[2]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.296 [get_ports {mem_dq[2]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.158 [get_ports {mem_dq[3]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.296 [get_ports {mem_dq[3]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.158 [get_ports {mem_dq[4]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.296 [get_ports {mem_dq[4]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.158 [get_ports {mem_dq[5]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.296 [get_ports {mem_dq[5]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.158 [get_ports {mem_dq[6]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.296 [get_ports {mem_dq[6]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.158 [get_ports {mem_dq[7]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.296 [get_ports {mem_dq[7]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.158 [get_ports {mem_dq[8]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.296 [get_ports {mem_dq[8]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.158 [get_ports {mem_dq[9]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.296 [get_ports {mem_dq[9]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.158 [get_ports {mem_dq[10]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.296 [get_ports {mem_dq[10]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.158 [get_ports {mem_dq[11]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.296 [get_ports {mem_dq[11]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.158 [get_ports {mem_dq[12]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.296 [get_ports {mem_dq[12]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.158 [get_ports {mem_dq[13]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.296 [get_ports {mem_dq[13]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.158 [get_ports {mem_dq[14]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.296 [get_ports {mem_dq[14]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.158 [get_ports {mem_dq[15]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.296 [get_ports {mem_dq[15]}]


#**************************************************************
# Set Output Delay
#**************************************************************

set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[3]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[3]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[4]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[4]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[5]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[5]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[6]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[6]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[7]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[7]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[8]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[8]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[9]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[9]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[10]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[10]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[11]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[11]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_a[12]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_a[12]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_ba[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_ba[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_ba[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_ba[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_ba[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_ba[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_cas_n[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_cas_n[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_cke[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_cke[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_cs_n[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_cs_n[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.341 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.322 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.341 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.322 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.341 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.322 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.341 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.322 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.051 [get_ports {mem_dqs[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.282 [get_ports {mem_dqs[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.051 [get_ports {mem_dqs[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.282 [get_ports {mem_dqs[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_odt[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_odt[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_ras_n[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_ras_n[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  2.027 [get_ports {mem_we_n[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  1.407 [get_ports {mem_we_n[0]}]


#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[0]_IN}] -group [get_clocks {mem_dqs[0]_OUT mem_dqs_n[0]_OUT}] 
set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[1]_IN}] -group [get_clocks {mem_dqs[1]_OUT mem_dqs_n[1]_OUT}] 
set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[0]_IN}] -group [get_clocks {mem_dqs[0]_OUT mem_dqs_n[0]_OUT}] 
set_clock_groups -physically_exclusive -group [get_clocks {mem_dqs[1]_IN}] -group [get_clocks {mem_dqs[1]_OUT mem_dqs_n[1]_OUT}] 


#**************************************************************
# Set False Path
#**************************************************************

set_false_path  -fall_from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {mem_ck[0]}]
set_false_path  -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]
set_false_path  -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {mem_dqs[0]_IN}]
set_false_path  -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {mem_dqs[1]_IN}]
set_false_path  -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {*_IN}]
set_false_path  -fall_from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {mem_ck[0]}]
set_false_path  -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]
set_false_path  -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {mem_dqs[0]_IN}]
set_false_path  -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {mem_dqs[1]_IN}]
set_false_path  -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {*_IN}]
set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
set_false_path -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_ports {{mem_a[0]} {mem_a[10]} {mem_a[11]} {mem_a[12]} {mem_a[1]} {mem_a[2]} {mem_a[3]} {mem_a[4]} {mem_a[5]} {mem_a[6]} {mem_a[7]} {mem_a[8]} {mem_a[9]} {mem_ba[0]} {mem_ba[1]} {mem_ba[2]} {mem_cas_n[0]} {mem_cke[0]} {mem_cs_n[0]} {mem_odt[0]} {mem_ras_n[0]} {mem_we_n[0]}}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*s0|*}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]
set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*]}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_clocks {mem_dqs[0]_OUT}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_clocks {mem_dqs[1]_OUT}]
set_false_path -from [get_keepers {ddr3:ddr3_inst|ddr3_0002:ddr3_inst|ddr3_p0:p0|ddr3_p0_acv_hard_memphy:umemphy|hphy_inst~FF_39}] -to [get_keepers {rst}]
set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}]
set_false_path -from [get_registers {*altera_jtag_src_crosser:*|sink_data_buffer*}] -to [get_registers {*altera_jtag_src_crosser:*|src_data*}]
set_false_path -fall_from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_ports {{mem_a[0]} {mem_a[10]} {mem_a[11]} {mem_a[12]} {mem_a[1]} {mem_a[2]} {mem_a[3]} {mem_a[4]} {mem_a[5]} {mem_a[6]} {mem_a[7]} {mem_a[8]} {mem_a[9]} {mem_ba[0]} {mem_ba[1]} {mem_ba[2]} {mem_cas_n[0]} {mem_cke[0]} {mem_cs_n[0]} {mem_odt[0]} {mem_ras_n[0]} {mem_we_n[0]}}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*ddio_out*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_IN_READ_EN_DFF}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_IN_READ_EN_DFF}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*vfifo~INC_WR_PTR_DFF}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|vfifo~QVLD_IN_DFF}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_OUT_RDATA_VALID_DFF}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|vfifo~QVLD_IN_DFF}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~RD_LATENCY_DFF*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*ddio_out*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*altdq_dqs2_inst|*output_path_gen[*].ddio_out*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*altdq_dqs2_inst|extra_output_pad_gen[*].ddio_out*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*c0|hmc_inst~FF_*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*phase_align_os~DFF*}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*s0|*}] -to [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]
set_false_path -from [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*s0|*hphy_bridge_s0_translator|av_readdata_pre[*]}]
set_false_path -to [get_ports {mem_dqs_n[0]}]
set_false_path -to [get_ports {mem_dqs_n[1]}]
set_false_path -to [get_ports {mem_ck[0]}]
set_false_path -to [get_ports {mem_ck_n[0]}]
set_false_path -to [get_ports {mem_reset_n}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_clocks {mem_dqs[0]_OUT}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_clocks {mem_dqs[1]_OUT}]
set_false_path -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|dqs_enable_ctrl~*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|dqs_delay_chain~POSTAMBLE_DFF}]


#**************************************************************
# Set Multicycle Path
#**************************************************************

set_multicycle_path -setup -start -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 5
set_multicycle_path -hold -start -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 4
set_multicycle_path -hold -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 1
set_multicycle_path -setup -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 2
set_multicycle_path -hold -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 1
set_multicycle_path -setup -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 2
set_multicycle_path -hold -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 1
set_multicycle_path -setup -start -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 5
set_multicycle_path -hold -start -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 4
set_multicycle_path -hold -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 1
set_multicycle_path -setup -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 2
set_multicycle_path -hold -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_afi_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_phy_clk}] 1
set_multicycle_path -setup -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 2
set_multicycle_path -hold -end -from  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_config_clk}]  -to  [get_clocks {ddr3_inst|ddr3_inst|pll0|pll_avl_clk}] 1
set_multicycle_path -setup -end -to [get_registers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*}] 4
set_multicycle_path -hold -end -to [get_registers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*uio_pads|*uaddr_cmd_pads|*clock_gen[*].umem_ck_pad|*}] 4
set_multicycle_path -setup -end -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_IN_READ_EN_FULL_DFF}] 2
set_multicycle_path -hold -end -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*lfifo~LFIFO_IN_READ_EN_FULL_DFF}] 1
set_multicycle_path -setup -end -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|*read_fifo~READ_ADDRESS_DFF}] 2
set_multicycle_path -hold -end -from [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|hphy_inst~FF_*}] -to [get_keepers {*:ddr3_inst|*:ddr3_inst|*p0|*altdq_dqs2_inst|*read_fifo~READ_ADDRESS_DFF}] 1
set_multicycle_path -setup -end -to [get_registers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]}] 2
set_multicycle_path -hold -end -to [get_registers {*:ddr3_inst|*:ddr3_inst|*p0|*umemphy|*phy_csr_inst|*csr_register_0004[*]}] 1


#**************************************************************
# Set Maximum Delay
#**************************************************************

set_max_delay -from [get_ports {mem_dq[0]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[1]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[2]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[3]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[4]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[5]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[6]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[7]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[8]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[9]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[10]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[11]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[12]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[13]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[14]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[15]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] 0.000


#**************************************************************
# Set Minimum Delay
#**************************************************************

set_min_delay -from [get_ports {mem_dq[0]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[1]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[2]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[3]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[4]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[5]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[6]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[7]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[8]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[9]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[10]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[11]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[12]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[13]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[14]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667
set_min_delay -from [get_ports {mem_dq[15]}] -to [get_keepers {{*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:ddr3_inst|*:ddr3_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}}] -1.667


#**************************************************************
# Set Input Transition
#**************************************************************