library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library design; use design.all; entity bench_top is end entity bench_top; architecture RTL of bench_top is constant SIM_SPEEDUP : natural := 2; signal clk_hw : std_logic; signal rst_hw : std_logic; signal ws2812_out : std_logic_vector(4 - 1 downto 0); signal uart_tx : std_logic; begin top_inst : entity design.top generic map( f_clk => 24_000_000 / SIM_SPEEDUP, ROWS => 4, COLUMNS => 4 ) port map( clk_hw => clk_hw, rst_hw => rst_hw, ws2812_out => ws2812_out, uart_rx => uart_tx ); clock_driver : process constant period : time := (1 sec / 24_000_000); begin clk_hw <= '0'; wait for period / 2; clk_hw <= '1'; wait for period / 2; end process clock_driver; test : process is constant UART_BITTIME : time := 1 sec / 115200 / SIM_SPEEDUP; procedure uart_transmit(data : in std_logic_vector(7 downto 0)) is begin uart_tx <= '0'; wait for UART_BITTIME; for i in 0 to 7 loop uart_tx <= data(i); wait for UART_BITTIME; end loop; uart_tx <= '1'; wait for UART_BITTIME; end procedure uart_transmit; begin rst_hw <= '0'; uart_tx <= '1'; wait until clk_hw = '1'; wait until clk_hw = '1'; rst_hw <= '1'; wait until clk_hw = '1'; wait for UART_BITTIME * 13; wait until clk_hw = '1'; -- Write LED data (cmd 0x00) uart_transmit(x"00"); uart_transmit(x"00"); -- Start address 0 uart_transmit(x"00"); uart_transmit(x"00"); -- Write two LEDs uart_transmit(x"02"); uart_transmit(x"01"); -- First LED uart_transmit(x"02"); uart_transmit(x"03"); uart_transmit(x"11"); uart_transmit(x"12"); uart_transmit(x"13"); uart_transmit(x"21"); uart_transmit(x"22"); uart_transmit(x"23"); uart_transmit(x"31"); uart_transmit(x"32"); uart_transmit(x"33"); uart_transmit(x"a1"); -- Second LED uart_transmit(x"a2"); uart_transmit(x"a3"); uart_transmit(x"b1"); uart_transmit(x"b2"); uart_transmit(x"b3"); uart_transmit(x"c1"); uart_transmit(x"c2"); uart_transmit(x"c3"); uart_transmit(x"d1"); uart_transmit(x"d2"); uart_transmit(x"d3"); -- Render (cmd 0x01) uart_transmit(x"01"); wait; end process test; end architecture RTL;