library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ram is generic( WIDTH : natural := 8; DEPTH : natural := 4 ); port( clk : in std_logic; addr_a : in std_logic_vector(DEPTH - 1 downto 0); data_out_a : out std_logic_vector(WIDTH - 1 downto 0); data_in_a : in std_logic_vector(WIDTH - 1 downto 0); we_a : in std_logic; addr_b : in std_logic_vector(DEPTH - 1 downto 0); data_out_b : out std_logic_vector(WIDTH - 1 downto 0) ); end entity ram; architecture rtl of ram is type memory_t is array (0 to integer(2**DEPTH) - 1) of std_logic_vector(WIDTH - 1 downto 0); signal memory : memory_t; begin ram_p : process(clk) is begin if (rising_edge(clk)) then data_out_a <= memory(to_integer(unsigned(addr_a))); if (we_a = '1') then memory(to_integer(unsigned(addr_a))) <= data_in_a; end if; data_out_b <= memory(to_integer(unsigned(addr_b))); end if; end process ram_p; end architecture rtl;