library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity synchronizer is generic(COUNT : integer := 1); port( clk : in std_logic; rst : in std_logic; dIn : in std_logic_vector(COUNT - 1 downto 0); dOut : out std_logic_vector(COUNT - 1 downto 0) ); end entity synchronizer; architecture RTL of synchronizer is signal temp : std_logic_vector(COUNT - 1 downto 0); begin synch : process(rst, clk) is begin for i in 0 to COUNT - 1 loop if rst = '1' then temp(i) <= '0'; dOut(i) <= '0'; elsif rising_edge(clk) then temp(i) <= dIn(i); dOut(i) <= temp(i); end if; end loop; end process synch; end architecture RTL;