trashernet/cocotb/cocotb_trashernet_phy.vhd

-- -------------------------------------------------------------------------- --
--               TRASHERNET - A Trashy Ethernet Stack for FPGAs               --
-- -------------------------------------------------------------------------- --
-- bench_trashernet_phy.vhd : Cocotb test bench for the PHY
-- -------------------------------------------------------------------------- --
-- Author       : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License      : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library trashernet;
use trashernet.trashernet_pkg.all;

entity cocotb_trashernet_phy is
end entity cocotb_trashernet_phy;

architecture bench of cocotb_trashernet_phy is
	signal clk     : std_logic;
	signal phy_clk : std_logic;
	signal rst     : std_logic;
	signal phy_out : phy_out_t;
	signal phy_in  : phy_in_t;
	signal rx_p    : std_logic;
	signal tx_p    : std_logic;
	signal tx_n    : std_logic;

	-- Cocotb interface
	signal coco_dut_rxd : std_logic_vector(7 downto 0); -- RX data
	signal coco_dut_rxs : std_logic := '0'; -- RX toggle
	signal coco_dut_rxa : std_logic;    -- RX active

	signal coco_tb_txd : std_logic_vector(7 downto 0); -- TX data
	signal coco_tb_txs : std_logic := '0'; -- TX toggle
	signal coco_tb_txa : std_logic := '0'; -- TX done toggle

begin
	-- Instantiate design
	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
		generic map(
			F_CLK     => 49000000,
			F_CLK_PHY => 100000000
		)
		port map(
			clk     => clk,
			phy_clk => phy_clk,
			rst     => rst,
			phy_out => phy_out,
			phy_in  => phy_in,
			rx_p    => rx_p,
			tx_p    => tx_p,
			tx_n    => tx_n
		);

	-- Create infrastructure
	clock_driver : process
		constant period : time := 20 ns;
	begin
		clk <= '0';
		wait for period / 2;
		clk <= '1';
		wait for period / 2;
	end process clock_driver;

	phy_clock_driver : process
		constant period : time := 10 ns;
	begin
		phy_clk <= '0';
		wait for period / 2;
		phy_clk <= '1';
		wait for period / 2;
	end process phy_clock_driver;

	-- Cocotb adapter (ETH)
	test : process is
	begin
		rx_p <= '0';

		loop
			wait on coco_tb_txs;

			for j in coco_tb_txd'low to coco_tb_txd'high loop
				rx_p <= not coco_tb_txd(j);
				wait for 50 ns;
				rx_p <= coco_tb_txd(j);
				wait for 50 ns;
			end loop;
			coco_tb_txa <= not coco_tb_txa;
		end loop;
	end process test;

	receiver : process is
	begin
		wait until rising_edge(clk);
		if phy_out.rx_data_valid then
			coco_dut_rxd <= phy_out.rx_data;
			coco_dut_rxs <= not coco_dut_rxs;
		end if;
	end process receiver;
	coco_dut_rxa <= phy_out.rx_active;
end architecture bench;