diff --git a/bench/bench_trashernet_mac.vhd b/bench/bench_trashernet_mac.vhd index 4e7cdfe..3bc6563 100644 --- a/bench/bench_trashernet_mac.vhd +++ b/bench/bench_trashernet_mac.vhd @@ -32,16 +32,8 @@ architecture bench of bench_trashernet_mac is signal tx_p : std_logic; signal tx_n : std_logic; - signal rx_mac_data : byte; - signal rx_mac_valid : std_logic; - signal rx_mac_crc_ok : std_logic; - signal rx_mac_crc_error : std_logic; - signal rx_mac_header_rcv : std_logic; - signal tx_mac_data : byte; - signal tx_mac_data_en : std_logic; - signal tx_mac_data_ack : std_logic; - signal rx_header : mac_header_fields; - signal tx_header : mac_header_fields; + signal mac_out : mac_out_t; + signal mac_in : mac_in_t; constant TEST_BENCH_LOOPBACK : boolean := true; @@ -64,20 +56,12 @@ begin trashernet_mac_inst : entity trashernet.trashernet_mac port map( - clk => clk, - rst => rst, - phy_out => phy_out, - phy_in => phy_in, - rx_header => rx_header, - rx_mac_header_rcv => rx_mac_header_rcv, - rx_mac_data => rx_mac_data, - rx_mac_valid => rx_mac_valid, - rx_mac_crc_ok => rx_mac_crc_ok, - rx_mac_crc_error => rx_mac_crc_error, - tx_header => tx_header, - tx_mac_data => tx_mac_data, - tx_mac_data_en => tx_mac_data_en, - tx_mac_data_ack => tx_mac_data_ack + clk => clk, + rst => rst, + phy_out => phy_out, + phy_in => phy_in, + mac_out => mac_out, + mac_in => mac_in ); clock_driver : process @@ -147,34 +131,34 @@ begin if phy_out.rx_data_valid then report "[PHY] RX byte: " & to_hstring(phy_out.rx_data); end if; - if rx_mac_valid then - report "[MAC] RX byte: " & to_hstring(rx_mac_data); + if mac_out.rx_mac_valid then + report "[MAC] RX byte: " & to_hstring(mac_out.rx_mac_data); end if; - if rx_mac_crc_ok then + if mac_out.rx_mac_crc_ok then report "[MAC] RX CRC OK"; end if; - if rx_mac_crc_error then + if mac_out.rx_mac_crc_error then report "[MAC] RX CRC error"; end if; end process receiver; mac_tx : process is begin - tx_mac_data <= x"11"; - tx_header.mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67"); - tx_header.mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7"); - tx_header.mac_ethertype <= (x"01", x"00"); - tx_mac_data_en <= '0'; + mac_in.tx_mac_data <= x"11"; + mac_in.tx_header.mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67"); + mac_in.tx_header.mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7"); + mac_in.tx_header.mac_ethertype <= (x"01", x"00"); + mac_in.tx_mac_data_en <= '0'; wait until rst = '0'; wait for 100 ns; - tx_mac_data_en <= '1'; - wait until rising_edge(tx_mac_data_ack); - wait until rising_edge(tx_mac_data_ack); - wait until rising_edge(tx_mac_data_ack); + mac_in.tx_mac_data_en <= '1'; + wait until rising_edge(mac_out.tx_mac_data_ack); + wait until rising_edge(mac_out.tx_mac_data_ack); + wait until rising_edge(mac_out.tx_mac_data_ack); wait until rising_edge(clk); - tx_mac_data_en <= '0'; + mac_in.tx_mac_data_en <= '0'; wait; end process mac_tx; diff --git a/trashernet/trashernet_mac.vhd b/trashernet/trashernet_mac.vhd index 549108b..db548d3 100644 --- a/trashernet/trashernet_mac.vhd +++ b/trashernet/trashernet_mac.vhd @@ -18,25 +18,16 @@ use work.trashernet_pkg.all; entity trashernet_mac is port( -- Global - clk : in std_logic; -- Global clock - rst : in std_logic; -- Asynchronous reset + clk : in std_logic; -- Global clock + rst : in std_logic; -- Asynchronous reset -- PHY signals - phy_out : in phy_out_t; -- PHY application IF (out of PHY) - phy_in : out phy_in_t; -- PHY application IF (into PHY) + phy_out : in phy_out_t; -- PHY application IF (out of PHY) + phy_in : out phy_in_t; -- PHY application IF (into PHY) - -- MAC signals - rx_header : out mac_header_fields; -- RX MAC Header Data - rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid - rx_mac_data : out byte; -- Ethernet data (after Ethertype) - rx_mac_valid : out std_logic; -- `rx_mac` values (headers + data) are valid - rx_mac_crc_ok : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields) - rx_mac_crc_error : out std_logic; -- End of packet, CRC invalid - - tx_header : in mac_header_fields; -- TX MAC Header Data - tx_mac_data : in byte; -- Payload - tx_mac_data_en : in std_logic; -- Start (and keep) transmitting a frame - tx_mac_data_ack : out std_logic -- The byte on `tx_mac_data` has been latched. Update to next word. + -- MAC application IF + mac_out : out mac_out_t; -- MAC application IF (out of MAC) + mac_in : in mac_in_t -- MAC application IF (into MAC) ); end entity trashernet_mac; @@ -47,7 +38,7 @@ begin rx : block type state_t is (HEAD, PAYLOAD); - constant HEAD_LENGTH : integer := rx_header.mac_destination'length + rx_header.mac_source'length + rx_header.mac_ethertype'length; + constant HEAD_LENGTH : integer := mac_out.rx_header.mac_destination'length + mac_out.rx_header.mac_source'length + mac_out.rx_header.mac_ethertype'length; constant CRC_LENGTH : integer := 4; signal state : state_t; signal sr_head : byte_vector(0 to HEAD_LENGTH - 1); @@ -81,28 +72,28 @@ begin main : process(clk, rst) is begin if rst then - byte_count <= 0; - rx_mac_valid <= '0'; - rx_mac_crc_error <= '0'; - rx_mac_crc_ok <= '0'; - rx_mac_header_rcv <= '0'; - crc_clear <= '0'; + byte_count <= 0; + mac_out.rx_mac_valid <= '0'; + mac_out.rx_mac_crc_error <= '0'; + mac_out.rx_mac_crc_ok <= '0'; + mac_out.rx_mac_header_rcv <= '0'; + crc_clear <= '0'; elsif rising_edge(clk) then - rx_mac_valid <= '0'; - rx_mac_crc_error <= '0'; - rx_mac_crc_ok <= '0'; - rx_mac_header_rcv <= '0'; - crc_clear <= '0'; + mac_out.rx_mac_valid <= '0'; + mac_out.rx_mac_crc_error <= '0'; + mac_out.rx_mac_crc_ok <= '0'; + mac_out.rx_mac_header_rcv <= '0'; + crc_clear <= '0'; case state is when HEAD => if phy_out.rx_data_valid then sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & phy_out.rx_data; if byte_count = (HEAD_LENGTH - 1) then - state <= PAYLOAD; - byte_count <= 0; - rx_mac_header_rcv <= '1'; + state <= PAYLOAD; + byte_count <= 0; + mac_out.rx_mac_header_rcv <= '1'; end if; if (byte_count /= BYTE_COUNT_MAX) then @@ -113,17 +104,17 @@ begin if phy_out.rx_data_valid then sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data; if byte_count = CRC_LENGTH then - rx_mac_valid <= '1'; + mac_out.rx_mac_valid <= '1'; else byte_count <= byte_count + 1; end if; end if; if not phy_out.rx_active then - rx_mac_crc_ok <= crc_ok; - rx_mac_crc_error <= not crc_ok; + mac_out.rx_mac_crc_ok <= crc_ok; + mac_out.rx_mac_crc_error <= not crc_ok; end if; if phy_out.rx_error then - rx_mac_crc_error <= '1'; + mac_out.rx_mac_crc_error <= '1'; end if; end case; @@ -135,10 +126,10 @@ begin end if; end process main; - rx_header.mac_destination <= sr_head(0 to 5); - rx_header.mac_source <= sr_head(6 to 11); - rx_header.mac_ethertype <= sr_head(12 to 13); - rx_mac_data <= sr_payload(0); + mac_out.rx_header.mac_destination <= sr_head(0 to 5); + mac_out.rx_header.mac_source <= sr_head(6 to 11); + mac_out.rx_header.mac_ethertype <= sr_head(12 to 13); + mac_out.rx_mac_data <= sr_payload(0); end block rx; @@ -146,7 +137,7 @@ begin type tx_state_t is (IDLE, HEADER, DATA, TXCRC); signal tx_state : tx_state_t; - signal sr : byte_vector(0 to tx_header.mac_destination'length + tx_header.mac_source'length + tx_header.mac_ethertype'length - 1); + signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1); constant BIT_CNT_MAX : integer := sr'high; signal byte_cnt : integer range 0 to BIT_CNT_MAX; @@ -173,11 +164,11 @@ begin tx_main : process(clk, rst) is begin if rst then - tx_mac_data_ack <= '0'; + mac_out.tx_mac_data_ack <= '0'; elsif rising_edge(clk) then - tx_mac_data_ack <= '0'; - crc_valid <= '0'; + mac_out.tx_mac_data_ack <= '0'; + crc_valid <= '0'; if phy_out.tx_data_ack then sr <= sr(sr'low + 1 to sr'high) & x"00"; @@ -188,7 +179,7 @@ begin end if; case tx_state is when IDLE => - if not phy_out.tx_active and tx_mac_data_en then + if not phy_out.tx_active and mac_in.tx_mac_data_en then sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5"); byte_cnt <= 7; tx_state <= HEADER; @@ -196,7 +187,7 @@ begin when HEADER => if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete - sr <= tx_header.mac_destination & tx_header.mac_source & tx_header.mac_ethertype; + sr <= mac_in.tx_header.mac_destination & mac_in.tx_header.mac_source & mac_in.tx_header.mac_ethertype; crc_valid <= '1'; byte_cnt <= BIT_CNT_MAX; tx_state <= DATA; @@ -204,9 +195,9 @@ begin when DATA => if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete - if tx_mac_data_en then - sr(0) <= tx_mac_data; - tx_mac_data_ack <= '1'; + if mac_in.tx_mac_data_en then + sr(0) <= mac_in.tx_mac_data; + mac_out.tx_mac_data_ack <= '1'; else sr(0 to 3) <= (crc(7 downto 0), crc(15 downto 8), crc(23 downto 16), crc(31 downto 24)); byte_cnt <= 4 - 1; diff --git a/trashernet/trashernet_pkg.vhd b/trashernet/trashernet_pkg.vhd index e88af23..3426b32 100644 --- a/trashernet/trashernet_pkg.vhd +++ b/trashernet/trashernet_pkg.vhd @@ -12,10 +12,12 @@ library ieee; use ieee.std_logic_1164.all; package trashernet_pkg is + -- General types subtype byte is std_logic_vector(7 downto 0); type byte_vector is array (natural range <>) of byte; + + -- MAC specific types subtype mac_addr_t is byte_vector(0 to 5); - subtype ip_addr_t is byte_vector(0 to 3); subtype ethertype_t is byte_vector(0 to 1); type mac_header_fields is record @@ -24,6 +26,9 @@ package trashernet_pkg is mac_ethertype : ethertype_t; -- Ethertype or length end record mac_header_fields; + -- IP specific types + subtype ip_addr_t is byte_vector(0 to 3); + -- PHY interface type phy_in_t is record tx_data : byte; -- TX Data @@ -40,6 +45,25 @@ package trashernet_pkg is carrier_detect : std_logic; -- Carrier detected rx_error : std_logic; -- Receive error end record phy_out_t; + + -- MAC interface + type mac_in_t is record + tx_header : mac_header_fields; -- TX MAC Header Data + tx_mac_data : byte; -- Payload + tx_mac_data_en : std_logic; -- Start (and keep) transmitting a frame + end record mac_in_t; + type mac_out_t is record + rx_header : mac_header_fields; -- RX MAC Header Data + rx_mac_header_rcv : std_logic; -- `rx_mac` header have been received and are valid + + rx_mac_data : byte; -- Ethernet data (after Ethertype) + rx_mac_valid : std_logic; -- `rx_mac` values (headers + data) are valid + tx_mac_data_ack : std_logic; -- The byte on `tx_mac_data` has been latched. Update to next word. + + rx_mac_crc_ok : std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields) + rx_mac_crc_error : std_logic; -- End of packet, CRC invalid + end record mac_out_t; + end package trashernet_pkg; package body trashernet_pkg is