From 1a41120afa960794378862ddbd29c2a87126cd9b Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Thu, 27 Oct 2022 17:02:53 +0200 Subject: [PATCH] bench: Clarify HWITL interface creation for local testing --- cocotb/hw_itl.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/cocotb/hw_itl.py b/cocotb/hw_itl.py index 6dbc301..2cc9b1b 100644 --- a/cocotb/hw_itl.py +++ b/cocotb/hw_itl.py @@ -17,9 +17,11 @@ import zlib ''' # Set up virtual device using -sudo ip link add virt0 type dummy -sudo ip link set up virt0 -sudo ip addr add 192.168.2.10/24 dev virt0 +sudo ip link add dev veth1 type veth peer name veth2 +sudo ip link set up veth1 +sudo ip link set up veth2 +sudo ip addr add 192.168.2.1/24 dev veth1 +sudo ip link set promisc on dev veth1 ''' class MacDevReceiver(): @@ -30,9 +32,6 @@ class MacDevReceiver(): self.dev = dev self.mac_rx_ev = Event() - print("Setting IF to promisc mode...") - os.system("ip link set promisc on dev {}".format(dev)) - ETH_P_ALL=3 self.macdev=socket.socket(socket.AF_PACKET, socket.SOCK_RAW, socket.htons(ETH_P_ALL)) self.macdev.bind((dev, 0)) @@ -83,7 +82,7 @@ async def hwitl(dut): await eth_rx.start() # Start local monitors - macdev_receiver = MacDevReceiver(dut, eth_tx, eth_rx, "virt0") + macdev_receiver = MacDevReceiver(dut, eth_tx, eth_rx, "veth2") # Wait for VHDL part to be ready await Edge(dut.bench_ready)