bench: Clarify HWITL interface creation for local testing
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5f7704cf63
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@ -17,9 +17,11 @@ import zlib
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'''
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'''
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# Set up virtual device using
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# Set up virtual device using
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sudo ip link add virt0 type dummy
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sudo ip link add dev veth1 type veth peer name veth2
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sudo ip link set up virt0
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sudo ip link set up veth1
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sudo ip addr add 192.168.2.10/24 dev virt0
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sudo ip link set up veth2
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sudo ip addr add 192.168.2.1/24 dev veth1
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sudo ip link set promisc on dev veth1
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'''
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'''
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class MacDevReceiver():
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class MacDevReceiver():
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@ -30,9 +32,6 @@ class MacDevReceiver():
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self.dev = dev
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self.dev = dev
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self.mac_rx_ev = Event()
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self.mac_rx_ev = Event()
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print("Setting IF to promisc mode...")
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os.system("ip link set promisc on dev {}".format(dev))
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ETH_P_ALL=3
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ETH_P_ALL=3
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self.macdev=socket.socket(socket.AF_PACKET, socket.SOCK_RAW, socket.htons(ETH_P_ALL))
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self.macdev=socket.socket(socket.AF_PACKET, socket.SOCK_RAW, socket.htons(ETH_P_ALL))
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self.macdev.bind((dev, 0))
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self.macdev.bind((dev, 0))
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@ -83,7 +82,7 @@ async def hwitl(dut):
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await eth_rx.start()
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await eth_rx.start()
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# Start local monitors
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# Start local monitors
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macdev_receiver = MacDevReceiver(dut, eth_tx, eth_rx, "virt0")
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macdev_receiver = MacDevReceiver(dut, eth_tx, eth_rx, "veth2")
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# Wait for VHDL part to be ready
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# Wait for VHDL part to be ready
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await Edge(dut.bench_ready)
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await Edge(dut.bench_ready)
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