fpga/trashernet
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Fix code formatting

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This commit is contained in:
Markus Koch 2021-09-04 19:33:44 +02:00
parent 743d2465d9
commit 1bff61d24a
2 changed files with 5 additions and 5 deletions
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6
bench/bench_crc.vhd
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@ -28,9 +28,9 @@ architecture bench of bench_crc is
begin begin
crc_inst : entity trashernet.crc crc_inst : entity trashernet.crc
generic map( generic map(
POLYNOMIAL => POLYNOMIAL, POLYNOMIAL => POLYNOMIAL,
START => x"FFFFFFFF", START => x"FFFFFFFF",
FINAL_XOR => x"FFFFFFFF", FINAL_XOR => x"FFFFFFFF",
REVERSE_OUT => true REVERSE_OUT => true
) )
port map( port map(

4
trashernet/trashernet_phy_cdc.vhd
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@ -27,11 +27,11 @@ entity trashernet_phy_cdc is
rst : in std_logic; -- Asynchronous reset rst : in std_logic; -- Asynchronous reset
-- System interface -- System interface
rx_data : out byte; -- RX Data rx_data : out byte; -- RX Data
rx_data_valid : out std_logic; -- RX Data valid rx_data_valid : out std_logic; -- RX Data valid
rx_active : out std_logic; -- RX of packet in progress rx_active : out std_logic; -- RX of packet in progress
tx_data : in byte; -- TX Data tx_data : in byte; -- TX Data
tx_data_en : in std_logic; -- Transmitter enable tx_data_en : in std_logic; -- Transmitter enable
tx_data_ack : out std_logic; -- Latched data_tx tx_data_ack : out std_logic; -- Latched data_tx
tx_active : out std_logic; -- Transmission in progress tx_active : out std_logic; -- Transmission in progress