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bench: Test MAC TX

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This commit is contained in:
Markus Koch 2021-09-04 19:15:45 +02:00
parent 2bee387081
commit 35093bba85
1 changed files with 75 additions and 27 deletions
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56
bench/bench_trashernet_mac.vhd
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@ -34,6 +34,15 @@ architecture bench of bench_trashernet_mac is
signal rx_mac_valid : std_logic; signal rx_mac_valid : std_logic;
signal rx_mac_crc_ok : std_logic; signal rx_mac_crc_ok : std_logic;
signal rx_mac_crc_error : std_logic; signal rx_mac_crc_error : std_logic;
signal rx_mac_header_rcv : std_logic;
signal tx_mac_destination : mac_addr_t;
signal tx_mac_source : mac_addr_t;
signal tx_mac_ethertype : ethertype_t;
signal tx_mac_data : byte;
signal tx_mac_data_en : std_logic;
signal tx_mac_data_ack : std_logic;
constant TEST_BENCH_LOOPBACK : boolean := true;
begin begin
trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
@ -51,6 +60,7 @@ begin
tx_data => tx_data, tx_data => tx_data,
tx_data_en => tx_data_en, tx_data_en => tx_data_en,
tx_data_ack => tx_data_ack, tx_data_ack => tx_data_ack,
tx_active => tx_active,
carrier_detect => carrier_detect, carrier_detect => carrier_detect,
rx_error => rx_error, rx_error => rx_error,
rx_p => rx_p, rx_p => rx_p,
@ -76,8 +86,15 @@ begin
rx_mac_ethertype => rx_mac_ethertype, rx_mac_ethertype => rx_mac_ethertype,
rx_mac_data => rx_mac_data, rx_mac_data => rx_mac_data,
rx_mac_valid => rx_mac_valid, rx_mac_valid => rx_mac_valid,
rx_mac_header_rcv => rx_mac_header_rcv,
rx_mac_crc_ok => rx_mac_crc_ok, rx_mac_crc_ok => rx_mac_crc_ok,
rx_mac_crc_error => rx_mac_crc_error rx_mac_crc_error => rx_mac_crc_error,
tx_mac_destination => tx_mac_destination,
tx_mac_source => tx_mac_source,
tx_mac_ethertype => tx_mac_ethertype,
tx_mac_data => tx_mac_data,
tx_mac_data_en => tx_mac_data_en,
tx_mac_data_ack => tx_mac_data_ack
); );
clock_driver : process clock_driver : process
@ -98,14 +115,23 @@ begin
wait for period / 2; wait for period / 2;
end process phy_clock_driver; end process phy_clock_driver;
test : process is rstsim : process is
begin begin
rx_p <= '0';
rst <= '1'; rst <= '1';
wait for 20 ns; wait for 20 ns;
rst <= '0'; rst <= '0';
wait for 20 ns; wait for 20 ns;
wait;
end process rstsim;
loopbackmode : if TEST_BENCH_LOOPBACK generate
rx_p <= tx_p;
else generate
test : process is
begin
wait until rst = '0';
wait for 10 ns;
rx_p <= '0';
send_data(rx_p, byte_vector'( send_data(rx_p, byte_vector'(
x"55", x"55", x"55", x"D5", x"55", x"55", x"55", x"D5",
@ -130,6 +156,7 @@ begin
wait; wait;
end process test; end process test;
end generate loopbackmode;
receiver : process is receiver : process is
begin begin
@ -148,4 +175,25 @@ begin
end if; end if;
end process receiver; end process receiver;
mac_tx : process is
begin
tx_mac_data <= x"11";
tx_mac_destination <= (x"12", x"23", x"34", x"45", x"56", x"67");
tx_mac_source <= (x"a2", x"a3", x"a4", x"a5", x"a6", x"a7");
tx_mac_ethertype <= (x"01", x"00");
tx_mac_data_en <= '0';
wait until rst = '0';
wait for 100 ns;
tx_mac_data_en <= '1';
wait until rising_edge(tx_mac_data_ack);
wait until rising_edge(tx_mac_data_ack);
wait until rising_edge(tx_mac_data_ack);
wait until rising_edge(clk);
tx_mac_data_en <= '0';
wait;
end process mac_tx;
end architecture bench; end architecture bench;