From 4bce111d69883fc52a6446dd3c4354d6dfe541d3 Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Sun, 4 Feb 2024 09:34:32 +0100 Subject: [PATCH] doc: Add synthesized size for PHY-only design --- README.MD | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/README.MD b/README.MD index e063ac6..6995e82 100644 --- a/README.MD +++ b/README.MD @@ -28,6 +28,14 @@ Notes: * The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice! * On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D +## Stats + +Sythesized for a Lattice LFXP2-5E FPGA using LSE / Diamond v3.12: + +| Configuration | Slices | LUT4 | Registers | +| ---------------- | ------ | ---- | --------- | +| `trashernet_phy` | 115 | 188 | 91 | + ## License This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.