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bench: Update PHY ports

master
Markus Koch 3 months ago
parent
commit
5a1363615f
  1. 6
      bench/bench_trashernet_mac.vhd
  2. 6
      bench/bench_trashernet_phy.vhd

6
bench/bench_trashernet_mac.vhd

@ -20,10 +20,12 @@ architecture bench of bench_trashernet_mac is
signal tx_data : std_logic_vector(7 downto 0);
signal tx_data_en : std_logic;
signal tx_data_ack : std_logic;
signal tx_active : std_logic;
signal carrier_detect : std_logic;
signal rx_error : std_logic;
signal rx_p : std_logic;
signal tx_p : std_logic;
signal tx_n : std_logic;
signal rx_mac_destination : mac_addr_t;
signal rx_mac_source : mac_addr_t;
@ -52,7 +54,8 @@ begin
carrier_detect => carrier_detect,
rx_error => rx_error,
rx_p => rx_p,
tx_p => tx_p
tx_p => tx_p,
tx_n => tx_n
);
trashernet_mac_inst : entity trashernet.trashernet_mac
@ -65,6 +68,7 @@ begin
tx_data => tx_data,
tx_data_en => tx_data_en,
tx_data_ack => tx_data_ack,
tx_active => tx_active,
carrier_detect => carrier_detect,
rx_error => rx_error,
rx_mac_destination => rx_mac_destination,

6
bench/bench_trashernet_phy.vhd

@ -24,6 +24,8 @@ architecture bench of bench_trashernet_phy is
signal rx_error : std_logic;
signal rx_p : std_logic;
signal tx_p : std_logic;
signal tx_active : std_logic;
signal tx_n : std_logic;
begin
trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
@ -41,10 +43,12 @@ begin
tx_data => tx_data,
tx_data_en => tx_data_en,
tx_data_ack => tx_data_ack,
tx_active => tx_active,
carrier_detect => carrier_detect,
rx_error => rx_error,
rx_p => rx_p,
tx_p => tx_p
tx_p => tx_p,
tx_n => tx_n
);
clock_driver : process

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