diff --git a/design/top_mac_test.vhd b/design/top_mac_test.vhd index b1f77ea..097ce36 100644 --- a/design/top_mac_test.vhd +++ b/design/top_mac_test.vhd @@ -68,7 +68,7 @@ architecture rtl of top_mac_test is signal mac_out : mac_out_t; signal mac_in : mac_in_t; - type status_t is (IDLE, TX, WAITDONE); + type status_t is (IDLE, TX); signal state : status_t; constant BYTE_CNT_MAX : integer := 100; signal byte_cnt : integer range 0 to BYTE_CNT_MAX; @@ -190,15 +190,11 @@ begin if mac_out.tx_mac_data_ack then if byte_cnt = 1 then mac_in.tx_mac_data_en <= '0'; - state <= WAITDONE; + state <= IDLE; else byte_cnt <= byte_cnt - 1; end if; end if; - when WAITDONE => - if mac_out.tx_active = '0' then - state <= IDLE; - end if; end case; end if;