diff --git a/bench/bench_pkg.vhd b/bench/bench_pkg.vhd new file mode 100644 index 0000000..cb3b9c9 --- /dev/null +++ b/bench/bench_pkg.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +library trashernet; +use trashernet.trashernet_types.all; + +package bench_pkg is + procedure send_data(signal rx_p : inout std_logic; constant data : in byte_vector); +end package bench_pkg; + +package body bench_pkg is + procedure send_data(signal rx_p : inout std_logic; constant data : in byte_vector) is + begin + for i in data'low to data'high loop + for j in data(i)'low to data(i)'high loop + rx_p <= not data(i)(j); + wait for 50 ns; + rx_p <= data(i)(j); + wait for 50 ns; + end loop; + end loop; + end procedure send_data; +end package body bench_pkg; diff --git a/bench/bench_trashernet_phy.vhd b/bench/bench_trashernet_phy.vhd new file mode 100644 index 0000000..78374d0 --- /dev/null +++ b/bench/bench_trashernet_phy.vhd @@ -0,0 +1,89 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.bench_pkg.all; + +library trashernet; +use trashernet.trashernet_types.all; + +entity bench_trashernet_phy is +end entity bench_trashernet_phy; + +architecture bench of bench_trashernet_phy is + signal clk : std_logic; + signal phy_clk : std_logic; + signal rst : std_logic; + signal rx_data : std_logic_vector(7 downto 0); + signal rx_data_valid : std_logic; + signal rx_active : std_logic; + signal tx_data : std_logic_vector(7 downto 0); + signal tx_data_en : std_logic; + signal tx_data_ack : std_logic; + signal carrier_detect : std_logic; + signal rx_error : std_logic; + signal rx_p : std_logic; + signal tx_p : std_logic; + +begin + trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc + generic map( + F_CLK => 49000000, + F_CLK_PHY => 100000000 + ) + port map( + clk => clk, + phy_clk => phy_clk, + rst => rst, + rx_data => rx_data, + rx_data_valid => rx_data_valid, + rx_active => rx_active, + tx_data => tx_data, + tx_data_en => tx_data_en, + tx_data_ack => tx_data_ack, + carrier_detect => carrier_detect, + rx_error => rx_error, + rx_p => rx_p, + tx_p => tx_p + ); + + clock_driver : process + constant period : time := 20 ns; + begin + clk <= '0'; + wait for period / 2; + clk <= '1'; + wait for period / 2; + end process clock_driver; + + phy_clock_driver : process + constant period : time := 10 ns; + begin + phy_clk <= '0'; + wait for period / 2; + phy_clk <= '1'; + wait for period / 2; + end process phy_clock_driver; + + test : process is + begin + rx_p <= '0'; + + rst <= '1'; + wait for 20 ns; + rst <= '0'; + wait for 20 ns; + + send_data(rx_p, byte_vector'(x"55", x"55", x"55", x"D5", x"12", x"34")); + wait; + end process test; + + receiver : process is + begin + wait until rising_edge(clk); + if rx_data_valid then + report "RX byte: " & to_hstring(rx_data); + end if; + end process receiver; + +end architecture bench;