From 7cb86523bab770f903f3f695bba58e4b0b5a01e2 Mon Sep 17 00:00:00 2001 From: Markus Perkins Date: Fri, 10 Oct 2025 16:05:38 +0200 Subject: [PATCH] rmii: Reset some more signals --- trashernet/trashernet_rmii.vhd | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/trashernet/trashernet_rmii.vhd b/trashernet/trashernet_rmii.vhd index 6999990..7b7fdde 100644 --- a/trashernet/trashernet_rmii.vhd +++ b/trashernet/trashernet_rmii.vhd @@ -82,7 +82,9 @@ begin rxp : process(rmii_rst, rmii_ref_clk) is begin if rmii_rst then - state <= IDLE; + state <= IDLE; + dibit_cnt <= 0; + sr <= (others => '0'); elsif rising_edge(rmii_ref_clk) then -- Shift in data bytes @@ -253,7 +255,10 @@ begin txp : process(rmii_ref_clk, rmii_rst) is begin if rmii_rst then - state <= IDLE; + state <= IDLE; + byte_cnt <= 0; + dibit_cnt <= 0; + sr <= (others => '-'); elsif rising_edge(rmii_ref_clk) then sr <= "00" & sr(sr'high downto 2); @@ -297,7 +302,7 @@ begin temp_tx_data_ack <= '1' when (state = DATA) and (byte_done = '1') and (temp_tx_data_en = '1') else '0'; temp_tx_active <= '1' when state = DATA else '0'; - rmii_txd <= sr(1 downto 0); + rmii_txd <= sr(rmii_txd'range); rmii_tx_en <= '1' when state = DATA else '0'; end block transmitter; end architecture rtl;