fpga/trashernet
1
0
Fork 0
Code Issues 7 Pull Requests 2 Releases 2 Wiki Activity

Clean up code formatting

Browse Source
This commit is contained in:
Markus Koch 2022-01-22 20:50:18 +01:00
parent 4e39e3b371
commit afb545cd02
2 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
trashernet/cdc_strobe.vhd
View File

@ -54,8 +54,7 @@ begin
); );
-- strobify -- strobify
b_toggle_last <= '0' when b_rst b_toggle_last <= '0' when b_rst else
else b_toggle when rising_edge(b_clk) b_toggle when rising_edge(b_clk);
;
b_out <= (b_toggle ?/= b_toggle_last); b_out <= (b_toggle ?/= b_toggle_last);
end architecture rtl; end architecture rtl;

2
trashernet/trashernet_phy.vhd
View File

@ -56,7 +56,7 @@ begin
signal bit_cnt : integer range 0 to 7; signal bit_cnt : integer range 0 to 7;
-- NLP supervision -- NLP supervision
constant NLP_TIMEOUT_CNT_MAX : integer := integer(round(real(F_CLK) * 16.0 * 10.0**(-3))); -- Every 16 ms constant NLP_TIMEOUT_CNT_MAX : integer := integer(round(real(F_CLK) * 16.0 * 10.0 ** (-3))); -- Every 16 ms
signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX; signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX;
begin begin
-- Synchronize RX input -- Synchronize RX input