phy: Refactor to use records for the application interface
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						cfac94136a
					
				@ -25,16 +25,9 @@ architecture bench of bench_trashernet_mac is
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	signal clk     : std_logic;
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						signal clk     : std_logic;
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	signal phy_clk : std_logic;
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						signal phy_clk : std_logic;
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	signal rst     : std_logic;
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						signal rst     : std_logic;
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	signal rx_data        : std_logic_vector(7 downto 0);
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	signal rx_data_valid  : std_logic;
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						signal phy_out : phy_out_t;
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	signal rx_active      : std_logic;
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						signal phy_in  : phy_in_t;
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	signal tx_data        : std_logic_vector(7 downto 0);
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	signal tx_data_en     : std_logic;
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	signal tx_data_ack    : std_logic;
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	signal tx_active      : std_logic;
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	signal tx_header      : mac_header_fields;
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	signal carrier_detect : std_logic;
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	signal rx_error       : std_logic;
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	signal rx_p    : std_logic;
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						signal rx_p    : std_logic;
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	signal tx_p    : std_logic;
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						signal tx_p    : std_logic;
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	signal tx_n    : std_logic;
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						signal tx_n    : std_logic;
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@ -48,6 +41,7 @@ architecture bench of bench_trashernet_mac is
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	signal tx_mac_data_en    : std_logic;
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						signal tx_mac_data_en    : std_logic;
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	signal tx_mac_data_ack   : std_logic;
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						signal tx_mac_data_ack   : std_logic;
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	signal rx_header         : mac_header_fields;
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						signal rx_header         : mac_header_fields;
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						signal tx_header         : mac_header_fields;
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	constant TEST_BENCH_LOOPBACK : boolean := true;
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						constant TEST_BENCH_LOOPBACK : boolean := true;
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@ -61,15 +55,8 @@ begin
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			clk     => clk,
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								clk     => clk,
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			phy_clk => phy_clk,
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								phy_clk => phy_clk,
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			rst     => rst,
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								rst     => rst,
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			rx_data        => rx_data,
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								phy_out => phy_out,
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			rx_data_valid  => rx_data_valid,
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								phy_in  => phy_in,
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			rx_active      => rx_active,
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			tx_data        => tx_data,
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			tx_data_en     => tx_data_en,
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			tx_data_ack    => tx_data_ack,
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			tx_active      => tx_active,
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			carrier_detect => carrier_detect,
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			rx_error       => rx_error,
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			rx_p    => rx_p,
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								rx_p    => rx_p,
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			tx_p    => tx_p,
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								tx_p    => tx_p,
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			tx_n    => tx_n
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								tx_n    => tx_n
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@ -79,19 +66,12 @@ begin
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		port map(
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							port map(
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			clk               => clk,
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								clk               => clk,
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			rst               => rst,
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								rst               => rst,
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			rx_data           => rx_data,
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								phy_out           => phy_out,
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			rx_data_valid     => rx_data_valid,
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								phy_in            => phy_in,
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			rx_active         => rx_active,
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			tx_data           => tx_data,
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			tx_data_en        => tx_data_en,
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			tx_data_ack       => tx_data_ack,
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			tx_active         => tx_active,
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			carrier_detect    => carrier_detect,
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			rx_error          => rx_error,
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			rx_header         => rx_header,
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								rx_header         => rx_header,
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								rx_mac_header_rcv => rx_mac_header_rcv,
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			rx_mac_data       => rx_mac_data,
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								rx_mac_data       => rx_mac_data,
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			rx_mac_valid      => rx_mac_valid,
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								rx_mac_valid      => rx_mac_valid,
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			rx_mac_header_rcv => rx_mac_header_rcv,
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			rx_mac_crc_ok     => rx_mac_crc_ok,
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								rx_mac_crc_ok     => rx_mac_crc_ok,
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			rx_mac_crc_error  => rx_mac_crc_error,
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								rx_mac_crc_error  => rx_mac_crc_error,
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			tx_header         => tx_header,
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								tx_header         => tx_header,
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@ -164,8 +144,8 @@ begin
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	receiver : process is
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						receiver : process is
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	begin
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						begin
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		wait until rising_edge(clk);
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							wait until rising_edge(clk);
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		if rx_data_valid then
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							if phy_out.rx_data_valid then
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			report "[PHY] RX byte: " & to_hstring(rx_data);
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								report "[PHY] RX byte: " & to_hstring(phy_out.rx_data);
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		end if;
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							end if;
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		if rx_mac_valid then
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							if rx_mac_valid then
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			report "[MAC] RX byte: " & to_hstring(rx_mac_data);
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								report "[MAC] RX byte: " & to_hstring(rx_mac_data);
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@ -25,19 +25,13 @@ architecture bench of bench_trashernet_phy is
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	signal clk            : std_logic;
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						signal clk            : std_logic;
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	signal phy_clk        : std_logic;
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						signal phy_clk        : std_logic;
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	signal rst            : std_logic;
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						signal rst            : std_logic;
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	signal rx_data        : std_logic_vector(7 downto 0);
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						signal phy_out : phy_out_t;
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	signal rx_data_valid  : std_logic;
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						signal phy_in : phy_in_t;
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	signal rx_active      : std_logic;
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	signal tx_data        : std_logic_vector(7 downto 0);
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	signal tx_data_en     : std_logic;
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	signal tx_data_ack    : std_logic;
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	signal carrier_detect : std_logic;
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	signal rx_error       : std_logic;
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	signal rx_p : std_logic;
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						signal rx_p : std_logic;
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	signal tx_p : std_logic;
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						signal tx_p : std_logic;
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	signal tx_active      : std_logic;
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	signal tx_n : std_logic;
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						signal tx_n : std_logic;
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begin
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					begin
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	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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						trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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		generic map(
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							generic map(
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@ -48,15 +42,8 @@ begin
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			clk => clk,
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								clk => clk,
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			phy_clk => phy_clk,
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								phy_clk => phy_clk,
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			rst => rst,
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								rst => rst,
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			rx_data        => rx_data,
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								phy_out => phy_out,
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			rx_data_valid  => rx_data_valid,
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								phy_in => phy_in,
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			rx_active      => rx_active,
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			tx_data        => tx_data,
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			tx_data_en     => tx_data_en,
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			tx_data_ack    => tx_data_ack,
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			tx_active      => tx_active,
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			carrier_detect => carrier_detect,
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			rx_error       => rx_error,
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			rx_p => rx_p,
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								rx_p => rx_p,
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			tx_p => tx_p,
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								tx_p => tx_p,
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			tx_n => tx_n
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								tx_n => tx_n
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@ -96,8 +83,8 @@ begin
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	receiver : process is
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						receiver : process is
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	begin
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						begin
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		wait until rising_edge(clk);
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							wait until rising_edge(clk);
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		if rx_data_valid then
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							if phy_out.rx_data_valid then
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			report "RX byte: " & to_hstring(rx_data);
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								report "RX byte: " & to_hstring(phy_out.rx_data);
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		end if;
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							end if;
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	end process receiver;
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						end process receiver;
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@ -22,17 +22,8 @@ entity trashernet_mac is
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		rst               : in  std_logic; -- Asynchronous reset
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							rst               : in  std_logic; -- Asynchronous reset
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		-- PHY signals
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							-- PHY signals
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		rx_data           : in  byte;   -- RX Data
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							phy_out           : in  phy_out_t; -- PHY application IF (out of PHY)
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		rx_data_valid     : in  std_logic; -- RX Data valid
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							phy_in            : out phy_in_t; -- PHY application IF (into PHY)
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		rx_active         : in  std_logic; -- RX of packet in progress
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		tx_data           : out byte;   -- TX Data
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		tx_data_en        : out std_logic; -- Transmitter enable
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		tx_data_ack       : in  std_logic; -- Latched data_tx
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		tx_active         : in  std_logic; -- Transmitter active
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		carrier_detect    : in  std_logic; -- Carrier detected
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		rx_error          : in  std_logic; -- Receive error
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		-- MAC signals
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							-- MAC signals
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		rx_header         : out mac_header_fields; -- RX MAC Header Data
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							rx_header         : out mac_header_fields; -- RX MAC Header Data
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@ -79,8 +70,8 @@ begin
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			port map(
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								port map(
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				clk        => clk,
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									clk        => clk,
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				rst        => rst,
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									rst        => rst,
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				data       => rx_data,
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									data       => phy_out.rx_data,
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				data_valid => rx_data_valid,
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									data_valid => phy_out.rx_data_valid,
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				crc_clear  => crc_clear,
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									crc_clear  => crc_clear,
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				crc_out    => crc
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									crc_out    => crc
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			);
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								);
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@ -106,8 +97,8 @@ begin
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				case state is
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									case state is
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					when HEAD =>
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										when HEAD =>
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						if rx_data_valid then
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											if phy_out.rx_data_valid then
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							sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & rx_data;
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												sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & phy_out.rx_data;
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							if byte_count = (HEAD_LENGTH - 1) then
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												if byte_count = (HEAD_LENGTH - 1) then
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								state             <= PAYLOAD;
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													state             <= PAYLOAD;
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								byte_count        <= 0;
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													byte_count        <= 0;
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@ -119,24 +110,24 @@ begin
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							end if;
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												end if;
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						end if;
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											end if;
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					when PAYLOAD =>
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										when PAYLOAD =>
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						if rx_data_valid then
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											if phy_out.rx_data_valid then
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							sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & rx_data;
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												sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data;
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							if byte_count = CRC_LENGTH then
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												if byte_count = CRC_LENGTH then
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								rx_mac_valid <= '1';
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													rx_mac_valid <= '1';
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							else
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												else
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								byte_count <= byte_count + 1;
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													byte_count <= byte_count + 1;
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							end if;
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												end if;
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						end if;
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											end if;
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						if not rx_active then
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											if not phy_out.rx_active then
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							rx_mac_crc_ok    <= crc_ok;
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												rx_mac_crc_ok    <= crc_ok;
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							rx_mac_crc_error <= not crc_ok;
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												rx_mac_crc_error <= not crc_ok;
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						end if;
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											end if;
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						if rx_error then
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											if phy_out.rx_error then
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							rx_mac_crc_error <= '1';
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												rx_mac_crc_error <= '1';
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						end if;
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											end if;
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				end case;
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									end case;
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				if (not rx_active) or rx_error then
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									if (not phy_out.rx_active) or phy_out.rx_error then
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					byte_count <= 0;
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										byte_count <= 0;
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					state      <= HEAD;
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										state      <= HEAD;
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					crc_clear  <= '1';
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										crc_clear  <= '1';
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@ -173,7 +164,7 @@ begin
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			port map(
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								port map(
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				clk        => clk,
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									clk        => clk,
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				rst        => rst,
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									rst        => rst,
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				data       => tx_data,
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									data       => phy_in.tx_data,
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				data_valid => crc_valid,
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									data_valid => crc_valid,
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				crc_clear  => crc_clear,
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									crc_clear  => crc_clear,
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				crc_out    => crc
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									crc_out    => crc
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@ -188,7 +179,7 @@ begin
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				tx_mac_data_ack <= '0';
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									tx_mac_data_ack <= '0';
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				crc_valid       <= '0';
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									crc_valid       <= '0';
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				if tx_data_ack then
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									if phy_out.tx_data_ack then
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					sr        <= sr(sr'low + 1 to sr'high) & x"00";
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										sr        <= sr(sr'low + 1 to sr'high) & x"00";
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					crc_valid <= '1';
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										crc_valid <= '1';
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					if byte_cnt /= 0 then
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										if byte_cnt /= 0 then
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@ -197,14 +188,14 @@ begin
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				end if;
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									end if;
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				case tx_state is
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									case tx_state is
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					when IDLE =>
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										when IDLE =>
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						if not tx_active and tx_mac_data_en then
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											if not phy_out.tx_active and tx_mac_data_en then
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							sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5");
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												sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5");
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							byte_cnt   <= 7;
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												byte_cnt   <= 7;
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							tx_state   <= HEADER;
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												tx_state   <= HEADER;
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						end if;
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											end if;
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					when HEADER =>
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										when HEADER =>
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						if (tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
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											if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
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							sr        <= tx_header.mac_destination & tx_header.mac_source & tx_header.mac_ethertype;
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												sr        <= tx_header.mac_destination & tx_header.mac_source & tx_header.mac_ethertype;
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							crc_valid <= '1';
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												crc_valid <= '1';
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							byte_cnt  <= BIT_CNT_MAX;
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												byte_cnt  <= BIT_CNT_MAX;
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@ -212,7 +203,7 @@ begin
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						end if;
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											end if;
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					when DATA =>
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										when DATA =>
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						if (tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete
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											if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete
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							if tx_mac_data_en then
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												if tx_mac_data_en then
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								sr(0)           <= tx_mac_data;
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													sr(0)           <= tx_mac_data;
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								tx_mac_data_ack <= '1';
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													tx_mac_data_ack <= '1';
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@ -224,15 +215,15 @@ begin
 | 
				
			|||||||
						end if;
 | 
											end if;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
					when TXCRC =>
 | 
										when TXCRC =>
 | 
				
			||||||
						if (tx_data_ack = '1') and (byte_cnt = 0) then -- CRC TX complete
 | 
											if (phy_out.tx_data_ack = '1') and (byte_cnt = 0) then -- CRC TX complete
 | 
				
			||||||
							tx_state <= IDLE;
 | 
												tx_state <= IDLE;
 | 
				
			||||||
						end if;
 | 
											end if;
 | 
				
			||||||
				end case;
 | 
									end case;
 | 
				
			||||||
			end if;
 | 
								end if;
 | 
				
			||||||
		end process tx_main;
 | 
							end process tx_main;
 | 
				
			||||||
		tx_data_en <= '1' when tx_state /= IDLE else '0';
 | 
							phy_in.tx_data_en <= '1' when tx_state /= IDLE else '0';
 | 
				
			||||||
		crc_clear         <= '1' when tx_state = HEADER else '0';
 | 
							crc_clear         <= '1' when tx_state = HEADER else '0';
 | 
				
			||||||
		tx_data    <= sr(sr'low);
 | 
							phy_in.tx_data    <= sr(sr'low);
 | 
				
			||||||
	end block tx;
 | 
						end block tx;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
end architecture rtl;
 | 
					end architecture rtl;
 | 
				
			||||||
 | 
				
			|||||||
@ -25,18 +25,9 @@ entity trashernet_phy is
 | 
				
			|||||||
		clk     : in  std_logic;        -- Global clock
 | 
							clk     : in  std_logic;        -- Global clock
 | 
				
			||||||
		rst     : in  std_logic;        -- Asynchronous reset
 | 
							rst     : in  std_logic;        -- Asynchronous reset
 | 
				
			||||||
 | 
					
 | 
				
			||||||
		-- Eth
 | 
							-- PHY application interface
 | 
				
			||||||
		rx_data        : out byte;      -- RX Data
 | 
							phy_out : out phy_out_t;        -- PHY application IF (out)
 | 
				
			||||||
		rx_data_valid  : out std_logic; -- RX Data valid
 | 
							phy_in  : in  phy_in_t;         -- PHY application IF (in)
 | 
				
			||||||
		rx_active      : out std_logic; -- RX of packet in progress
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
		tx_data        : in  byte;      -- TX Data
 | 
					 | 
				
			||||||
		tx_data_en     : in  std_logic; -- Transmitter enable
 | 
					 | 
				
			||||||
		tx_data_ack    : out std_logic; -- Latched data_tx
 | 
					 | 
				
			||||||
		tx_active      : out std_logic; -- Transmission in progress
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
		carrier_detect : out std_logic; -- Carrier detected
 | 
					 | 
				
			||||||
		rx_error       : out std_logic; -- Receive error
 | 
					 | 
				
			||||||
 | 
					
 | 
				
			||||||
		-- Ethernet physical signals
 | 
							-- Ethernet physical signals
 | 
				
			||||||
		rx_p    : in  std_logic;
 | 
							rx_p    : in  std_logic;
 | 
				
			||||||
@ -69,7 +60,7 @@ begin
 | 
				
			|||||||
		signal nlp_timeout_cnt       : integer range 0 to NLP_TIMEOUT_CNT_MAX;
 | 
							signal nlp_timeout_cnt       : integer range 0 to NLP_TIMEOUT_CNT_MAX;
 | 
				
			||||||
	begin
 | 
						begin
 | 
				
			||||||
		-- Synchronize RX input
 | 
							-- Synchronize RX input
 | 
				
			||||||
		synchronizer_inst : entity work.synchronizer
 | 
							synchronizer_rxp_inst : entity work.synchronizer
 | 
				
			||||||
			port map(
 | 
								port map(
 | 
				
			||||||
				clk      => clk,
 | 
									clk      => clk,
 | 
				
			||||||
				rst      => rst,
 | 
									rst      => rst,
 | 
				
			||||||
@ -188,11 +179,11 @@ begin
 | 
				
			|||||||
				if rst then
 | 
									if rst then
 | 
				
			||||||
					demanchestization_state <= SYNC;
 | 
										demanchestization_state <= SYNC;
 | 
				
			||||||
					bit_stb                 <= '0';
 | 
										bit_stb                 <= '0';
 | 
				
			||||||
					rx_active               <= '0';
 | 
										phy_out.rx_active       <= '0';
 | 
				
			||||||
					rx_error                <= '0';
 | 
										phy_out.rx_error        <= '0';
 | 
				
			||||||
				elsif rising_edge(clk) then
 | 
									elsif rising_edge(clk) then
 | 
				
			||||||
					bit_stb          <= '0';
 | 
										bit_stb          <= '0';
 | 
				
			||||||
					rx_error <= '0';
 | 
										phy_out.rx_error <= '0';
 | 
				
			||||||
 | 
					
 | 
				
			||||||
					if (bit_ev /= NONE) then
 | 
										if (bit_ev /= NONE) then
 | 
				
			||||||
						case demanchestization_state is
 | 
											case demanchestization_state is
 | 
				
			||||||
@ -200,7 +191,7 @@ begin
 | 
				
			|||||||
								if (bit_ev = KEEP) then
 | 
													if (bit_ev = KEEP) then
 | 
				
			||||||
									bit_value               <= '1';
 | 
														bit_value               <= '1';
 | 
				
			||||||
									demanchestization_state <= DATA;
 | 
														demanchestization_state <= DATA;
 | 
				
			||||||
									rx_active               <= '1';
 | 
														phy_out.rx_active       <= '1';
 | 
				
			||||||
								end if;
 | 
													end if;
 | 
				
			||||||
							when DATA => -- @suppress: Condition outside of case allows to exit this state
 | 
												when DATA => -- @suppress: Condition outside of case allows to exit this state
 | 
				
			||||||
								bit_value <= not bit_value when bit_ev = TOGGLE else bit_value;
 | 
													bit_value <= not bit_value when bit_ev = TOGGLE else bit_value;
 | 
				
			||||||
@ -211,13 +202,13 @@ begin
 | 
				
			|||||||
					end if;
 | 
										end if;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
					if (bit_ev = ERROR) then
 | 
										if (bit_ev = ERROR) then
 | 
				
			||||||
						rx_error                <= '1';
 | 
											phy_out.rx_error        <= '1';
 | 
				
			||||||
						demanchestization_state <= ERROR;
 | 
											demanchestization_state <= ERROR;
 | 
				
			||||||
					end if;
 | 
										end if;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
					if (not transition_activity) then
 | 
										if (not transition_activity) then
 | 
				
			||||||
						demanchestization_state <= SYNC;
 | 
											demanchestization_state <= SYNC;
 | 
				
			||||||
						rx_active               <= '0';
 | 
											phy_out.rx_active       <= '0';
 | 
				
			||||||
					end if;
 | 
										end if;
 | 
				
			||||||
				end if;
 | 
									end if;
 | 
				
			||||||
			end process bit_recovery;
 | 
								end process bit_recovery;
 | 
				
			||||||
@ -227,16 +218,16 @@ begin
 | 
				
			|||||||
		bytizer : process(clk, rst) is
 | 
							bytizer : process(clk, rst) is
 | 
				
			||||||
		begin
 | 
							begin
 | 
				
			||||||
			if rst then
 | 
								if rst then
 | 
				
			||||||
				rx_data_valid <= '0';
 | 
									phy_out.rx_data_valid <= '0';
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			elsif rising_edge(clk) then
 | 
								elsif rising_edge(clk) then
 | 
				
			||||||
				rx_data_valid <= '0';
 | 
									phy_out.rx_data_valid <= '0';
 | 
				
			||||||
 | 
					
 | 
				
			||||||
				if rx_active then
 | 
									if phy_out.rx_active then
 | 
				
			||||||
					if (bit_stb) then
 | 
										if (bit_stb) then
 | 
				
			||||||
						rx_data <= bit_value & rx_data(rx_data'high downto rx_data'low + 1);
 | 
											phy_out.rx_data <= bit_value & phy_out.rx_data(phy_out.rx_data'high downto phy_out.rx_data'low + 1);
 | 
				
			||||||
						if (bit_cnt = 7) then
 | 
											if (bit_cnt = 7) then
 | 
				
			||||||
							rx_data_valid <= '1';
 | 
												phy_out.rx_data_valid <= '1';
 | 
				
			||||||
							bit_cnt               <= 0;
 | 
												bit_cnt               <= 0;
 | 
				
			||||||
						else
 | 
											else
 | 
				
			||||||
							bit_cnt <= bit_cnt + 1;
 | 
												bit_cnt <= bit_cnt + 1;
 | 
				
			||||||
@ -263,7 +254,7 @@ begin
 | 
				
			|||||||
				end if;
 | 
									end if;
 | 
				
			||||||
			end if;
 | 
								end if;
 | 
				
			||||||
		end process nlp_timeout_p;
 | 
							end process nlp_timeout_p;
 | 
				
			||||||
		carrier_detect <= '1' when nlp_timeout_cnt /= 0 else '0';
 | 
							phy_out.carrier_detect <= '1' when nlp_timeout_cnt /= 0 else '0';
 | 
				
			||||||
	end block receiver;
 | 
						end block receiver;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	-- -------------------------------------------------------------------------
 | 
						-- -------------------------------------------------------------------------
 | 
				
			||||||
@ -274,7 +265,7 @@ begin
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
		type tx_state_t is (IDLE, NLP, TX, IPG);
 | 
							type tx_state_t is (IDLE, NLP, TX, IPG);
 | 
				
			||||||
		signal tx_state  : tx_state_t;
 | 
							signal tx_state  : tx_state_t;
 | 
				
			||||||
		signal sr        : std_logic_vector(tx_data'range);
 | 
							signal sr        : std_logic_vector(phy_in.tx_data'range);
 | 
				
			||||||
		signal bit_stage : std_logic;
 | 
							signal bit_stage : std_logic;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
		constant BIT_CNT_MAX_NLP  : integer := 16000 / 100; -- 16 ms (timebase 100 ns)
 | 
							constant BIT_CNT_MAX_NLP  : integer := 16000 / 100; -- 16 ms (timebase 100 ns)
 | 
				
			||||||
@ -291,10 +282,10 @@ begin
 | 
				
			|||||||
				tx_state <= TX;
 | 
									tx_state <= TX;
 | 
				
			||||||
				tx_mode  <= ACTIVE;
 | 
									tx_mode  <= ACTIVE;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
				sr          <= tx_data;
 | 
									sr                  <= phy_in.tx_data;
 | 
				
			||||||
				bit_stage           <= '0';
 | 
									bit_stage           <= '0';
 | 
				
			||||||
				bit_cnt             <= BIT_CNT_MAX_DATA;
 | 
									bit_cnt             <= BIT_CNT_MAX_DATA;
 | 
				
			||||||
				tx_data_ack <= '1';
 | 
									phy_out.tx_data_ack <= '1';
 | 
				
			||||||
			end procedure transmit_byte;
 | 
								end procedure transmit_byte;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			procedure transmit_ipg is
 | 
								procedure transmit_ipg is
 | 
				
			||||||
@ -325,13 +316,13 @@ begin
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
		begin
 | 
							begin
 | 
				
			||||||
			if rst then
 | 
								if rst then
 | 
				
			||||||
				tx_data_ack <= '0';
 | 
									phy_out.tx_data_ack <= '0';
 | 
				
			||||||
				tx_stb_cnt          <= TX_STB_CNT_MAX;
 | 
									tx_stb_cnt          <= TX_STB_CNT_MAX;
 | 
				
			||||||
				tx_mode             <= OFF;
 | 
									tx_mode             <= OFF;
 | 
				
			||||||
				go_idle;
 | 
									go_idle;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
			elsif rising_edge(clk) then
 | 
								elsif rising_edge(clk) then
 | 
				
			||||||
				tx_data_ack <= '0';
 | 
									phy_out.tx_data_ack <= '0';
 | 
				
			||||||
 | 
					
 | 
				
			||||||
				if tx_stb_cnt = 0 then
 | 
									if tx_stb_cnt = 0 then
 | 
				
			||||||
					tx_stb_cnt <= TX_STB_CNT_MAX;
 | 
										tx_stb_cnt <= TX_STB_CNT_MAX;
 | 
				
			||||||
@ -351,7 +342,7 @@ begin
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
				case tx_state is
 | 
									case tx_state is
 | 
				
			||||||
					when IDLE =>
 | 
										when IDLE =>
 | 
				
			||||||
						if tx_data_en then -- New packet to TX
 | 
											if phy_in.tx_data_en then -- New packet to TX
 | 
				
			||||||
							transmit_byte;
 | 
												transmit_byte;
 | 
				
			||||||
							bit_stage  <= '1';
 | 
												bit_stage  <= '1';
 | 
				
			||||||
							tx_stb_cnt <= TX_STB_CNT_MAX; -- resync
 | 
												tx_stb_cnt <= TX_STB_CNT_MAX; -- resync
 | 
				
			||||||
@ -372,7 +363,7 @@ begin
 | 
				
			|||||||
							if (bit_stage = '1') then
 | 
												if (bit_stage = '1') then
 | 
				
			||||||
								sr <= '0' & sr(sr'high downto sr'low + 1);
 | 
													sr <= '0' & sr(sr'high downto sr'low + 1);
 | 
				
			||||||
								if bit_cnt = 0 then
 | 
													if bit_cnt = 0 then
 | 
				
			||||||
									if tx_data_en then
 | 
														if phy_in.tx_data_en then
 | 
				
			||||||
										transmit_byte;
 | 
															transmit_byte;
 | 
				
			||||||
									else
 | 
														else
 | 
				
			||||||
										transmit_ipg;
 | 
															transmit_ipg;
 | 
				
			||||||
@ -387,7 +378,7 @@ begin
 | 
				
			|||||||
				end case;
 | 
									end case;
 | 
				
			||||||
			end if;
 | 
								end if;
 | 
				
			||||||
		end process tx_main;
 | 
							end process tx_main;
 | 
				
			||||||
		tx_active <= '1' when tx_state /= IDLE else '0';
 | 
							phy_out.tx_active <= '1' when tx_state /= IDLE else '0';
 | 
				
			||||||
 | 
					
 | 
				
			||||||
		driver : process(clk, rst) is
 | 
							driver : process(clk, rst) is
 | 
				
			||||||
		begin
 | 
							begin
 | 
				
			||||||
 | 
				
			|||||||
@ -26,18 +26,9 @@ entity trashernet_phy_cdc is
 | 
				
			|||||||
		phy_clk : in  std_logic;        -- Clock for PHY (rx_p, tx_p)
 | 
							phy_clk : in  std_logic;        -- Clock for PHY (rx_p, tx_p)
 | 
				
			||||||
		rst     : in  std_logic;        -- Asynchronous reset
 | 
							rst     : in  std_logic;        -- Asynchronous reset
 | 
				
			||||||
 | 
					
 | 
				
			||||||
		-- System interface
 | 
							-- PHY application interface
 | 
				
			||||||
		rx_data        : out byte;      -- RX Data
 | 
							phy_out : out phy_out_t;        -- PHY application IF (out)
 | 
				
			||||||
		rx_data_valid  : out std_logic; -- RX Data valid
 | 
							phy_in  : in  phy_in_t;         -- PHY application IF (in)
 | 
				
			||||||
		rx_active      : out std_logic; -- RX of packet in progress
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
		tx_data        : in  byte;      -- TX Data
 | 
					 | 
				
			||||||
		tx_data_en     : in  std_logic; -- Transmitter enable
 | 
					 | 
				
			||||||
		tx_data_ack    : out std_logic; -- Latched data_tx
 | 
					 | 
				
			||||||
		tx_active      : out std_logic; -- Transmission in progress
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
		carrier_detect : out std_logic; -- Carrier detected
 | 
					 | 
				
			||||||
		rx_error       : out std_logic; -- Receive error
 | 
					 | 
				
			||||||
 | 
					
 | 
				
			||||||
		-- Ethernet physical signals
 | 
							-- Ethernet physical signals
 | 
				
			||||||
		rx_p    : in  std_logic;
 | 
							rx_p    : in  std_logic;
 | 
				
			||||||
@ -46,18 +37,11 @@ entity trashernet_phy_cdc is
 | 
				
			|||||||
	);
 | 
						);
 | 
				
			||||||
end entity trashernet_phy_cdc;
 | 
					end entity trashernet_phy_cdc;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
architecture RTL of trashernet_phy_cdc is
 | 
					architecture rtl of trashernet_phy_cdc is
 | 
				
			||||||
	-- PHY signals
 | 
						-- PHY signals
 | 
				
			||||||
	signal phy_rst     : std_logic;
 | 
						signal phy_rst     : std_logic;
 | 
				
			||||||
	signal phy_rx_data        : std_logic_vector(7 downto 0);
 | 
						signal phy_phy_out : phy_out_t;
 | 
				
			||||||
	signal phy_rx_data_valid  : std_logic;
 | 
						signal phy_phy_in  : phy_in_t;
 | 
				
			||||||
	signal phy_rx_active      : std_logic;
 | 
					 | 
				
			||||||
	signal phy_tx_data        : std_logic_vector(7 downto 0);
 | 
					 | 
				
			||||||
	signal phy_tx_data_en     : std_logic;
 | 
					 | 
				
			||||||
	signal phy_tx_data_ack    : std_logic;
 | 
					 | 
				
			||||||
	signal phy_carrier_detect : std_logic;
 | 
					 | 
				
			||||||
	signal phy_rx_error       : std_logic;
 | 
					 | 
				
			||||||
	signal phy_tx_active      : std_logic;
 | 
					 | 
				
			||||||
 | 
					
 | 
				
			||||||
	-- Helper signals
 | 
						-- Helper signals
 | 
				
			||||||
	signal rx_data_valid_i : std_logic;
 | 
						signal rx_data_valid_i : std_logic;
 | 
				
			||||||
@ -82,15 +66,8 @@ begin
 | 
				
			|||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			clk     => phy_clk,
 | 
								clk     => phy_clk,
 | 
				
			||||||
			rst     => phy_rst,
 | 
								rst     => phy_rst,
 | 
				
			||||||
			rx_data        => phy_rx_data,
 | 
								phy_out => phy_phy_out,
 | 
				
			||||||
			rx_data_valid  => phy_rx_data_valid,
 | 
								phy_in  => phy_phy_in,
 | 
				
			||||||
			rx_active      => phy_rx_active,
 | 
					 | 
				
			||||||
			tx_data        => phy_tx_data,
 | 
					 | 
				
			||||||
			tx_data_en     => phy_tx_data_en,
 | 
					 | 
				
			||||||
			tx_data_ack    => phy_tx_data_ack,
 | 
					 | 
				
			||||||
			tx_active      => phy_tx_active,
 | 
					 | 
				
			||||||
			carrier_detect => phy_carrier_detect,
 | 
					 | 
				
			||||||
			rx_error       => phy_rx_error,
 | 
					 | 
				
			||||||
			rx_p    => rx_p,
 | 
								rx_p    => rx_p,
 | 
				
			||||||
			tx_p    => tx_p,
 | 
								tx_p    => tx_p,
 | 
				
			||||||
			tx_n    => tx_n
 | 
								tx_n    => tx_n
 | 
				
			||||||
@ -103,11 +80,11 @@ begin
 | 
				
			|||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			clk      => phy_clk,
 | 
								clk      => phy_clk,
 | 
				
			||||||
			rst      => phy_rst,
 | 
								rst      => phy_rst,
 | 
				
			||||||
			data_in  => tx_data_en,
 | 
								data_in  => phy_in.tx_data_en,
 | 
				
			||||||
			data_out => phy_tx_data_en
 | 
								data_out => phy_phy_in.tx_data_en
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	phy_tx_data <= tx_data;             -- When tx_data_en is through the synchronizer, this should be stable (and in the other direction, it should only change when we don't read it anyways)
 | 
						phy_phy_in.tx_data <= phy_in.tx_data; -- When tx_data_en is through the synchronizer, this should be stable (and in the other direction, it should only change when we don't read it anyways)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	-- -------------------------------------------------------------------------
 | 
						-- -------------------------------------------------------------------------
 | 
				
			||||||
	-- Drives: System clock domain
 | 
						-- Drives: System clock domain
 | 
				
			||||||
@ -116,7 +93,7 @@ begin
 | 
				
			|||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			a_clk => phy_clk,
 | 
								a_clk => phy_clk,
 | 
				
			||||||
			a_rst => phy_rst,
 | 
								a_rst => phy_rst,
 | 
				
			||||||
			a_in  => phy_rx_data_valid,
 | 
								a_in  => phy_phy_out.rx_data_valid,
 | 
				
			||||||
			b_clk => clk,
 | 
								b_clk => clk,
 | 
				
			||||||
			b_rst => rst,
 | 
								b_rst => rst,
 | 
				
			||||||
			b_out => rx_data_valid_i
 | 
								b_out => rx_data_valid_i
 | 
				
			||||||
@ -125,10 +102,10 @@ begin
 | 
				
			|||||||
	rxdvff : process(clk, rst) is
 | 
						rxdvff : process(clk, rst) is
 | 
				
			||||||
	begin
 | 
						begin
 | 
				
			||||||
		if rst then
 | 
							if rst then
 | 
				
			||||||
			rx_data_valid <= '0';
 | 
								phy_out.rx_data_valid <= '0';
 | 
				
			||||||
		elsif rising_edge(clk) then
 | 
							elsif rising_edge(clk) then
 | 
				
			||||||
			rx_data_valid <= rx_data_valid_i;
 | 
								phy_out.rx_data_valid <= rx_data_valid_i;
 | 
				
			||||||
			rx_data       <= phy_rx_data; -- Data should be stable after the time it takes the _valid signal to go through the synchronizer
 | 
								phy_out.rx_data       <= phy_phy_out.rx_data; -- Data should be stable after the time it takes the _valid signal to go through the synchronizer
 | 
				
			||||||
		end if;
 | 
							end if;
 | 
				
			||||||
	end process rxdvff;
 | 
						end process rxdvff;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@ -136,44 +113,44 @@ begin
 | 
				
			|||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			a_clk => phy_clk,
 | 
								a_clk => phy_clk,
 | 
				
			||||||
			a_rst => phy_rst,
 | 
								a_rst => phy_rst,
 | 
				
			||||||
			a_in  => phy_rx_error,
 | 
								a_in  => phy_phy_out.rx_error,
 | 
				
			||||||
			b_clk => clk,
 | 
								b_clk => clk,
 | 
				
			||||||
			b_rst => rst,
 | 
								b_rst => rst,
 | 
				
			||||||
			b_out => rx_error
 | 
								b_out => phy_out.rx_error
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	synchronizer_rxa_inst : entity work.synchronizer
 | 
						synchronizer_rxa_inst : entity work.synchronizer
 | 
				
			||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			clk      => clk,
 | 
								clk      => clk,
 | 
				
			||||||
			rst      => rst,
 | 
								rst      => rst,
 | 
				
			||||||
			data_in  => phy_rx_active,
 | 
								data_in  => phy_phy_out.rx_active,
 | 
				
			||||||
			data_out => rx_active
 | 
								data_out => phy_out.rx_active
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	cdc_strobe_txack_inst : entity work.cdc_strobe
 | 
						cdc_strobe_txack_inst : entity work.cdc_strobe
 | 
				
			||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			a_clk => phy_clk,
 | 
								a_clk => phy_clk,
 | 
				
			||||||
			a_rst => phy_rst,
 | 
								a_rst => phy_rst,
 | 
				
			||||||
			a_in  => phy_tx_data_ack,
 | 
								a_in  => phy_phy_out.tx_data_ack,
 | 
				
			||||||
			b_clk => clk,
 | 
								b_clk => clk,
 | 
				
			||||||
			b_rst => rst,
 | 
								b_rst => rst,
 | 
				
			||||||
			b_out => tx_data_ack
 | 
								b_out => phy_out.tx_data_ack
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	synchronizer_crs_inst : entity work.synchronizer
 | 
						synchronizer_crs_inst : entity work.synchronizer
 | 
				
			||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			clk      => clk,
 | 
								clk      => clk,
 | 
				
			||||||
			rst      => rst,
 | 
								rst      => rst,
 | 
				
			||||||
			data_in  => phy_carrier_detect,
 | 
								data_in  => phy_phy_out.carrier_detect,
 | 
				
			||||||
			data_out => carrier_detect
 | 
								data_out => phy_out.carrier_detect
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	synchronizer_txa_inst : entity work.synchronizer
 | 
						synchronizer_txa_inst : entity work.synchronizer
 | 
				
			||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			clk      => clk,
 | 
								clk      => clk,
 | 
				
			||||||
			rst      => rst,
 | 
								rst      => rst,
 | 
				
			||||||
			data_in  => phy_tx_active,
 | 
								data_in  => phy_phy_out.tx_active,
 | 
				
			||||||
			data_out => tx_active
 | 
								data_out => phy_out.tx_active
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
end architecture RTL;
 | 
					end architecture rtl;
 | 
				
			||||||
 | 
				
			|||||||
@ -23,6 +23,23 @@ package trashernet_pkg is
 | 
				
			|||||||
		mac_source      : mac_addr_t;   -- Source MAC address
 | 
							mac_source      : mac_addr_t;   -- Source MAC address
 | 
				
			||||||
		mac_ethertype   : ethertype_t;  -- Ethertype or length
 | 
							mac_ethertype   : ethertype_t;  -- Ethertype or length
 | 
				
			||||||
	end record mac_header_fields;
 | 
						end record mac_header_fields;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						-- PHY interface
 | 
				
			||||||
 | 
						type phy_in_t is record
 | 
				
			||||||
 | 
							tx_data    : byte;              -- TX Data
 | 
				
			||||||
 | 
							tx_data_en : std_logic;         -- Transmitter enable
 | 
				
			||||||
 | 
						end record phy_in_t;
 | 
				
			||||||
 | 
						type phy_out_t is record
 | 
				
			||||||
 | 
							rx_data        : byte;          -- RX Data
 | 
				
			||||||
 | 
							rx_data_valid  : std_logic;     -- RX Data valid
 | 
				
			||||||
 | 
							rx_active      : std_logic;     -- RX of packet in progress
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							tx_data_ack    : std_logic;     -- Latched data_tx
 | 
				
			||||||
 | 
							tx_active      : std_logic;     -- Transmission in progress
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							carrier_detect : std_logic;     -- Carrier detected
 | 
				
			||||||
 | 
							rx_error       : std_logic;     -- Receive error
 | 
				
			||||||
 | 
						end record phy_out_t;
 | 
				
			||||||
end package trashernet_pkg;
 | 
					end package trashernet_pkg;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
package body trashernet_pkg is
 | 
					package body trashernet_pkg is
 | 
				
			||||||
 | 
				
			|||||||
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		Reference in New Issue
	
	Block a user