diff --git a/trashernet/trashernet_phy.vhd b/trashernet/trashernet_phy.vhd index ab08b8e..041caa9 100644 --- a/trashernet/trashernet_phy.vhd +++ b/trashernet/trashernet_phy.vhd @@ -3,6 +3,8 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; +use work.trashernet_types.all; + entity trashernet_phy is generic( F_CLK : in integer -- Clock frequency @@ -13,11 +15,11 @@ entity trashernet_phy is rst : in std_logic; -- Asynchronous reset -- Eth - rx_data : out std_logic_vector(7 downto 0); -- RX Data + rx_data : out byte; -- RX Data rx_data_valid : out std_logic; -- RX Data valid rx_active : out std_logic; -- RX of packet in progress - tx_data : in std_logic_vector(7 downto 0); -- TX Data + tx_data : in byte; -- TX Data tx_data_en : in std_logic; -- Transmitter enable tx_data_ack : out std_logic; -- Latched data_tx diff --git a/trashernet/trashernet_phy_cdc.vhd b/trashernet/trashernet_phy_cdc.vhd index a544764..3986323 100644 --- a/trashernet/trashernet_phy_cdc.vhd +++ b/trashernet/trashernet_phy_cdc.vhd @@ -2,6 +2,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use work.trashernet_types.all; + entity trashernet_phy_cdc is generic( F_CLK : in integer; -- Clock frequency of design IF @@ -14,11 +16,11 @@ entity trashernet_phy_cdc is rst : in std_logic; -- Asynchronous reset -- System interface - rx_data : out std_logic_vector(7 downto 0); -- RX Data + rx_data : out byte; -- RX Data rx_data_valid : out std_logic; -- RX Data valid rx_active : out std_logic; -- RX of packet in progress - tx_data : in std_logic_vector(7 downto 0); -- TX Data + tx_data : in byte; -- TX Data tx_data_en : in std_logic; -- Transmitter enable tx_data_ack : out std_logic; -- Latched data_tx