diff --git a/cocotb/cocotb_top_hwitl.vhd b/cocotb/cocotb_top_hwitl.vhd index e0b0e95..6b56add 100644 --- a/cocotb/cocotb_top_hwitl.vhd +++ b/cocotb/cocotb_top_hwitl.vhd @@ -32,7 +32,7 @@ architecture bench of cocotb_top_hwitl is -- Generic test bench signal bench_ready : std_logic := '0'; begin - top_mac_test_inst : entity top_hwitl (mac) -- TODO: I haven't managed to get configurations working with cocotb yet, so changing this line changes the test case :( + top_mac_test_inst : entity top_hwitl(eth) -- TODO: I haven't managed to get configurations working with cocotb yet, so changing this line changes the test case :( port map( clk => clk, rst_n => rst_n, diff --git a/design/top_hwitl.vhd b/design/top_hwitl.vhd index 47754c8..988382b 100644 --- a/design/top_hwitl.vhd +++ b/design/top_hwitl.vhd @@ -203,3 +203,132 @@ begin debug_data(1) <= tx_n; end architecture mac; + +-- -------------------------------------------------------------------------- -- +-- top_hwitl (eth) +-- -------------------------------------------------------------------------- -- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use ieee.math_real.all; + +library trashernet; +use trashernet.trashernet_pkg.all; + +architecture eth of top_hwitl is + component pll0 + port( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic + ); + end component pll0; + + constant F_CLK : integer := 50000000; + constant F_CLK_PHY : integer := 140000000; + + constant LED_BLINK : boolean_vector(led_n'range) := ( + 6 downto 2 => true, + others => false + ); + + constant ETH_CONFIG : configuration_t := ( + mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33") + ); + + signal rst : std_logic; + signal clk_phy : std_logic; + signal phy_pll_lock : std_logic; + + signal phy_out : phy_out_t; + signal phy_in : phy_in_t; + + signal mac_out : mac_out_t; + signal mac_in : mac_in_t; + + constant PROT_ARP : integer := 0; + constant PROT_IP : integer := 1; + constant ETHERNET_II_PROTOCOLS : ethernet_ii_protocol_vector := (PROT_ARP => ETHERNET_II_PROTOCOL_ARP, PROT_IP => ETHERNET_II_PROTOCOL_IP); + signal ethernet_i_out : ethernet_i_out_t; + signal ethernet_i_in : ethernet_i_in_t; + signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range); + signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range); +begin + trashernet_eth_inst : entity trashernet.trashernet_eth + generic map( + ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS + ) + port map( + clk => clk, + rst => rst, + mac_out => mac_out, + mac_in => mac_in, + config => ETH_CONFIG, + ethernet_i_out => ethernet_i_out, + ethernet_i_in => ethernet_i_in, + ethernet_ii_out => ethernet_ii_out, + ethernet_ii_in => ethernet_ii_in + ); + + trashernet_mac_inst : entity trashernet.trashernet_mac + port map( + clk => clk, + rst => rst, + phy_out => phy_out, + phy_in => phy_in, + mac_out => mac_out, + mac_in => mac_in + ); + + pll0_inst : pll0 + port map( + CLK => clk, + CLKOP => clk_phy, + LOCK => phy_pll_lock + ); + + trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc + generic map( + F_CLK => F_CLK, + F_CLK_PHY => F_CLK_PHY + ) + port map( + clk => clk, + phy_clk => clk_phy, + rst => rst, + phy_out => phy_out, + phy_in => phy_in, + rx_p => rx_p, + tx_p => tx_p, + tx_n => tx_n + ); + + reset_sync : process(clk, rst_n) is + begin + if (rst_n = '0') then + rst <= '1'; + elsif (rising_edge(clk)) then + rst <= '0'; + end if; + end process reset_sync; + + receiver : process(clk, rst) is + begin + if rst then + + elsif rising_edge(clk) then + if ethernet_i_out.rx_header_rcv then + report "RX ETH-I: " & to_string(to_integer(ethernet_i_out.rx_length)); + end if; + if (ethernet_ii_out(PROT_ARP).rx_header_rcv) then + report "RX ARP"; + end if; + if (ethernet_ii_out(PROT_IP).rx_header_rcv) then + report "RX IP"; + end if; + end if; + end process receiver; + +end architecture eth;