diff --git a/.library_mapping.xml b/.library_mapping.xml index 1851878..c99f4fd 100644 --- a/.library_mapping.xml +++ b/.library_mapping.xml @@ -1,35 +1,10 @@ - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/.project b/.project index 1b74eb5..be46c73 100644 --- a/.project +++ b/.project @@ -5,16 +5,6 @@ - - org.eclipse.ui.externaltools.ExternalToolBuilder - full,incremental, - - - LaunchConfigHandle - <project>/.externalToolBuilders/com.sigasi.hdt.toolchains.vunit.builder.launch - - - org.eclipse.xtext.ui.shared.xtextBuilder @@ -22,9 +12,9 @@ + com.sigasi.hdt.verilog.ui.verilogNature com.sigasi.hdt.vhdl.ui.vhdlNature org.eclipse.xtext.ui.shared.xtextNature - com.sigasi.hdt.toolchains.vunit.nature @@ -32,11 +22,6 @@ 2 virtual:/virtual - - Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt - 1 - sigasiresource:/vhdl/readme.txt - Common Libraries/IEEE 2 @@ -52,15 +37,5 @@ 2 sigasiresource:/vhdl/2008/STD - - Common Libraries/src - 2 - /usr/local/diamond/3.12/cae_library/simulation/vhdl/xp2/src - - - Common Libraries/vunit - 2 - PARENT-1-PROJECT_LOC/vunit - diff --git a/.settings/com.sigasi.hdt.toolchains.vunit.prefs b/.settings/com.sigasi.hdt.toolchains.vunit.prefs deleted file mode 100644 index 2014e9a..0000000 --- a/.settings/com.sigasi.hdt.toolchains.vunit.prefs +++ /dev/null @@ -1,2 +0,0 @@ -VUnitScriptLocation=vunit/run.py -eclipse.preferences.version=1 diff --git a/.settings/com.sigasi.hdt.verilog.linting.prefs b/.settings/com.sigasi.hdt.verilog.linting.prefs new file mode 100644 index 0000000..2da4424 --- /dev/null +++ b/.settings/com.sigasi.hdt.verilog.linting.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +isEnabled=true diff --git a/.settings/com.sigasi.hdt.verilog.version.prefs b/.settings/com.sigasi.hdt.verilog.version.prefs new file mode 100644 index 0000000..ac609e1 --- /dev/null +++ b/.settings/com.sigasi.hdt.verilog.version.prefs @@ -0,0 +1 @@ +=sv2012 diff --git a/.settings/com.sigasi.hdt.vhdl.linting.prefs b/.settings/com.sigasi.hdt.vhdl.linting.prefs new file mode 100644 index 0000000..2da4424 --- /dev/null +++ b/.settings/com.sigasi.hdt.vhdl.linting.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +isEnabled=true diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs index 368c019..42fec4f 100644 --- a/.settings/org.eclipse.core.resources.prefs +++ b/.settings/org.eclipse.core.resources.prefs @@ -1,5 +1,5 @@ eclipse.preferences.version=1 -encoding//Common\ Libraries/IEEE=utf-8 -encoding//Common\ Libraries/IEEE\ Synopsys=utf-8 -encoding//Common\ Libraries/STD=utf-8 -encoding/Common\ Libraries=utf-8 +encoding//Common\ Libraries/IEEE=UTF-8 +encoding//Common\ Libraries/IEEE\ Synopsys=UTF-8 +encoding//Common\ Libraries/STD=UTF-8 +encoding//Common\ Libraries=UTF-8 diff --git a/bench/bench_crc.vhd b/bench/bench_crc.vhd index 3bc35af..af2147f 100644 --- a/bench/bench_crc.vhd +++ b/bench/bench_crc.vhd @@ -19,12 +19,12 @@ end entity bench_crc; architecture bench of bench_crc is constant POLYNOMIAL : std_logic_vector(31 downto 0) := x"04C11DB7"; - signal clk : std_logic; - signal rst : std_logic; - signal data : std_logic_vector(7 downto 0); - signal data_valid : std_logic; - signal crc_clear : std_logic; - signal crc_out : std_logic_vector(POLYNOMIAL'range); + signal clk : std_logic; + signal rst : std_logic; + signal data : std_logic_vector(7 downto 0); + signal data_valid : std_logic; + signal crc_clear : std_logic; + signal crc_out : std_logic_vector(POLYNOMIAL'range); begin crc_inst : entity trashernet.crc generic map( diff --git a/bench/bench_pkg.vhd b/bench/bench_pkg.vhd index fe9ce39..86c4eb4 100644 --- a/bench/bench_pkg.vhd +++ b/bench/bench_pkg.vhd @@ -30,7 +30,7 @@ package body bench_pkg is wait for 50 ns; end loop; end loop; - wait for 16 us; -- IPG + wait for 16 us; -- IPG report "Frame TX complete"; end procedure send_data; end package body bench_pkg; diff --git a/bench/bench_trashernet_phy.vhd b/bench/bench_trashernet_phy.vhd index 33129ba..bd7d5a0 100644 --- a/bench/bench_trashernet_phy.vhd +++ b/bench/bench_trashernet_phy.vhd @@ -22,15 +22,14 @@ entity bench_trashernet_phy is end entity bench_trashernet_phy; architecture bench of bench_trashernet_phy is - signal clk : std_logic; - signal phy_clk : std_logic; - signal rst : std_logic; + signal clk : std_logic; + signal phy_clk : std_logic; + signal rst : std_logic; signal phy_out : phy_out_t; - signal phy_in : phy_in_t; - signal rx_p : std_logic; - signal tx_p : std_logic; - signal tx_n : std_logic; - + signal phy_in : phy_in_t; + signal rx_p : std_logic; + signal tx_p : std_logic; + signal tx_n : std_logic; begin trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc @@ -39,14 +38,14 @@ begin F_CLK_PHY => 100000000 ) port map( - clk => clk, + clk => clk, phy_clk => phy_clk, - rst => rst, + rst => rst, phy_out => phy_out, - phy_in => phy_in, - rx_p => rx_p, - tx_p => tx_p, - tx_n => tx_n + phy_in => phy_in, + rx_p => rx_p, + tx_p => tx_p, + tx_n => tx_n ); clock_driver : process diff --git a/design/ledcon.vhd b/design/ledcon.vhd index 5673199..0999f94 100644 --- a/design/ledcon.vhd +++ b/design/ledcon.vhd @@ -29,8 +29,8 @@ end entity ledcon; architecture RTL of ledcon is constant MS_CNT_MAX : integer := integer(round(real(F_CLK) * (1.0 * 10.0 ** (-3)))); - signal ms_cnt : integer range 0 to MS_CNT_MAX; - signal ms_tick : std_logic; + signal ms_cnt : integer range 0 to MS_CNT_MAX; + signal ms_tick : std_logic; begin mstimer : process(clk, rst) is begin @@ -50,7 +50,7 @@ begin ledblock : block constant LED_CNT_MAX : integer := 50; -- on time, in ms constant LED_CNT_MIN : integer := -50; -- off time, in ms - signal led_cnt : integer range LED_CNT_MIN to LED_CNT_MAX; + signal led_cnt : integer range LED_CNT_MIN to LED_CNT_MAX; begin ledgen : if BLINK(i) generate ledproc : process(clk, rst) is diff --git a/design/top_hwitl.vhd b/design/top_hwitl.vhd index 835fa89..23f38b5 100644 --- a/design/top_hwitl.vhd +++ b/design/top_hwitl.vhd @@ -57,13 +57,13 @@ architecture mac of top_hwitl is signal mac_out : mac_out_t; signal mac_in : mac_in_t; - type status_t is (IDLE, TX); - signal state : status_t; + type status_t is (IDLE, TX); + signal state : status_t; constant BYTE_CNT_MAX : integer := 100; - signal byte_cnt : integer range 0 to BYTE_CNT_MAX; + signal byte_cnt : integer range 0 to BYTE_CNT_MAX; constant TMO_MAX : integer := integer(round((real(F_CLK) * 0.25))) - 1; - signal tmo : integer range 0 to TMO_MAX; + signal tmo : integer range 0 to TMO_MAX; begin trashernet_mac_inst : entity trashernet.trashernet_mac port map( @@ -206,10 +206,10 @@ architecture eth of top_hwitl is PROT_ARP => ETHERNET_II_PROTOCOL_ARP, PROT_IPV4 => ETHERNET_II_PROTOCOL_IPV4 ); - signal ethernet_i_out : ethernet_i_out_t; - signal ethernet_i_in : ethernet_i_in_t; - signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range); - signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range); + signal ethernet_i_out : ethernet_i_out_t; + signal ethernet_i_in : ethernet_i_in_t; + signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range); + signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range); signal arp_out : arp_out_t; signal arp_in : arp_in_t; @@ -217,14 +217,14 @@ architecture eth of top_hwitl is signal ipv4_out : ipv4_out_t; signal ipv4_in : ipv4_in_t; - constant IPROT_ICMP : integer := 0; - constant IPROT_UDP : integer := 1; - constant IPV4_PROTOCOLS : ipv4_protocol_vector := ( + constant IPROT_ICMP : integer := 0; + constant IPROT_UDP : integer := 1; + constant IPV4_PROTOCOLS : ipv4_protocol_vector := ( IPROT_ICMP => IPV4_PROTOCOL_ICMP, IPROT_UDP => IPV4_PROTOCOL_UDP ); - signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range); - signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range); + signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range); + signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range); signal udp_out : udp_out_t; signal udp_in : udp_in_t; diff --git a/design/top_mac_test.vhd b/design/top_mac_test.vhd index 097ce36..0a259ac 100644 --- a/design/top_mac_test.vhd +++ b/design/top_mac_test.vhd @@ -68,16 +68,16 @@ architecture rtl of top_mac_test is signal mac_out : mac_out_t; signal mac_in : mac_in_t; - type status_t is (IDLE, TX); - signal state : status_t; + type status_t is (IDLE, TX); + signal state : status_t; constant BYTE_CNT_MAX : integer := 100; - signal byte_cnt : integer range 0 to BYTE_CNT_MAX; + signal byte_cnt : integer range 0 to BYTE_CNT_MAX; signal button_n_sync : std_logic_vector(button_n'range); signal button : std_logic_vector(button_n'range); constant TMO_MAX : integer := integer(round((real(F_CLK) * 0.25))) - 1; - signal tmo : integer range 0 to TMO_MAX; + signal tmo : integer range 0 to TMO_MAX; begin trashernet_mac_inst : entity trashernet.trashernet_mac port map( @@ -190,7 +190,7 @@ begin if mac_out.tx_mac_data_ack then if byte_cnt = 1 then mac_in.tx_mac_data_en <= '0'; - state <= IDLE; + state <= IDLE; else byte_cnt <= byte_cnt - 1; end if; diff --git a/design/top_pingable.vhd b/design/top_pingable.vhd index 3d6c15c..842b714 100644 --- a/design/top_pingable.vhd +++ b/design/top_pingable.vhd @@ -79,10 +79,10 @@ architecture rtl of top_pingable is PROT_ARP => ETHERNET_II_PROTOCOL_ARP, PROT_IPV4 => ETHERNET_II_PROTOCOL_IPV4 ); - signal ethernet_i_out : ethernet_i_out_t; - signal ethernet_i_in : ethernet_i_in_t; - signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range); - signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range); + signal ethernet_i_out : ethernet_i_out_t; + signal ethernet_i_in : ethernet_i_in_t; + signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range); + signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range); signal arp_out : arp_out_t; signal arp_in : arp_in_t; @@ -90,12 +90,12 @@ architecture rtl of top_pingable is signal ipv4_out : ipv4_out_t; signal ipv4_in : ipv4_in_t; - constant IPROT_ICMP : integer := 0; - constant IPV4_PROTOCOLS : ipv4_protocol_vector := ( + constant IPROT_ICMP : integer := 0; + constant IPV4_PROTOCOLS : ipv4_protocol_vector := ( IPROT_ICMP => IPV4_PROTOCOL_ICMP ); - signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range); - signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range); + signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range); + signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range); signal button_n_sync : std_logic_vector(button_n'range); signal button : std_logic_vector(button_n'range); diff --git a/trashernet/fifo.vhd b/trashernet/fifo.vhd index a5af238..f08e2c7 100644 --- a/trashernet/fifo.vhd +++ b/trashernet/fifo.vhd @@ -34,11 +34,11 @@ entity fifo is end entity fifo; architecture rtl of fifo is - type memory_t is array (natural range <>) of std_logic_vector(data_in'range); - signal memory : memory_t(0 to DEPTH - 1); + type memory_t is array (natural range <>) of std_logic_vector(data_in'range); + signal memory : memory_t(0 to DEPTH - 1); subtype memory_pointer_t is integer range 0 to DEPTH - 1; - subtype usage_counter_t is integer range 0 to DEPTH; + subtype usage_counter_t is integer range 0 to DEPTH; signal read_pointer : memory_pointer_t; signal write_pointer : memory_pointer_t; diff --git a/trashernet/trashernet_arp.vhd b/trashernet/trashernet_arp.vhd index c63d7c4..62f3d62 100644 --- a/trashernet/trashernet_arp.vhd +++ b/trashernet/trashernet_arp.vhd @@ -64,8 +64,8 @@ architecture rtl of trashernet_arp is begin resolver : block - type resolver_state_t is (IDLE, QUERY_MAC); - signal state : resolver_state_t; + type resolver_state_t is (IDLE, QUERY_MAC); + signal state : resolver_state_t; signal query_mac_found : std_logic; signal query_timeout : std_logic := '0'; -- TODO: Implement @@ -146,19 +146,19 @@ begin signal sr : byte_vector(0 to BYTECOUNT_ADDRESSES - 1); constant SR_HEAD_OFFSET : integer := BYTECOUNT_ADDRESSES - BYTECOUNT_HEAD; - alias sr_head_htype is sr(SR_HEAD_OFFSET + 0 to SR_HEAD_OFFSET + 1); - alias sr_head_ptype is sr(SR_HEAD_OFFSET + 2 to SR_HEAD_OFFSET + 3); - alias sr_head_hlen is sr(SR_HEAD_OFFSET + 4); - alias sr_head_plen is sr(SR_HEAD_OFFSET + 5); - alias sr_head_oper is sr(SR_HEAD_OFFSET + 6 to SR_HEAD_OFFSET + 7); + alias sr_head_htype is sr(SR_HEAD_OFFSET + 0 to SR_HEAD_OFFSET + 1); + alias sr_head_ptype is sr(SR_HEAD_OFFSET + 2 to SR_HEAD_OFFSET + 3); + alias sr_head_hlen is sr(SR_HEAD_OFFSET + 4); + alias sr_head_plen is sr(SR_HEAD_OFFSET + 5); + alias sr_head_oper is sr(SR_HEAD_OFFSET + 6 to SR_HEAD_OFFSET + 7); constant SR_ADDRESSES_OFFSET : integer := -8; - alias sr_addresses_sha is sr(8 + SR_ADDRESSES_OFFSET to 13 + SR_ADDRESSES_OFFSET); - alias sr_addresses_spa is sr(14 + SR_ADDRESSES_OFFSET to 17 + SR_ADDRESSES_OFFSET); - alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET); -- @suppress "Unused declaration": We don't need to check this as this is already done by the MAC - alias sr_addresses_tpa is sr(24 + SR_ADDRESSES_OFFSET to 27 + SR_ADDRESSES_OFFSET); + alias sr_addresses_sha is sr(8 + SR_ADDRESSES_OFFSET to 13 + SR_ADDRESSES_OFFSET); + alias sr_addresses_spa is sr(14 + SR_ADDRESSES_OFFSET to 17 + SR_ADDRESSES_OFFSET); + alias sr_addresses_tha is sr(18 + SR_ADDRESSES_OFFSET to 23 + SR_ADDRESSES_OFFSET); -- @suppress "Unused declaration": We don't need to check this as this is already done by the MAC + alias sr_addresses_tpa is sr(24 + SR_ADDRESSES_OFFSET to 27 + SR_ADDRESSES_OFFSET); - type state_t is (HEAD, ADDRESSES, WAITCRC, SENDREPLY, IGNORE); + type state_t is (HEAD, ADDRESSES, WAITCRC, SENDREPLY, IGNORE); signal state : state_t; signal bytecount : integer range 0 to BYTECOUNT_ADDRESSES; signal shifted : std_logic; @@ -240,7 +240,7 @@ begin state <= HEAD; end if; - when IGNORE => -- @suppress "Dead state 'IGNORE'": Outgoing transition provided outside of case statement (on RX ok/err) + when IGNORE => -- @suppress "Dead state 'IGNORE'": Outgoing transition provided outside of case statement (on RX ok/err) null; end case; end if; @@ -253,14 +253,14 @@ begin end block rx; tx : block - signal sr : byte_vector(0 to 27); - signal arp_reply_preload : byte_vector(sr'range); - signal arp_request_preload : byte_vector(sr'range); - constant BYTECOUNT_MAX : integer := sr'length + 1; - signal bytecount : integer range 0 to BYTECOUNT_MAX; + signal sr : byte_vector(0 to 27); + signal arp_reply_preload : byte_vector(sr'range); + signal arp_request_preload : byte_vector(sr'range); + constant BYTECOUNT_MAX : integer := sr'length + 1; + signal bytecount : integer range 0 to BYTECOUNT_MAX; - type state_t is (IDLE, TRANSMIT); - signal state : state_t; + type state_t is (IDLE, TRANSMIT); + signal state : state_t; begin arp_reply_preload <= HTYPE & PTYPE & HLEN & PLEN & OPER_REPLY & -- Header diff --git a/trashernet/trashernet_eth.vhd b/trashernet/trashernet_eth.vhd index 3195958..0827b90 100644 --- a/trashernet/trashernet_eth.vhd +++ b/trashernet/trashernet_eth.vhd @@ -46,11 +46,11 @@ architecture rtl of trashernet_eth is signal tx_data_ack_i : std_logic; begin rx : block - constant SEL_ETH_I : integer := ethernet_ii_out'low - 1; - constant SEL_ETH_NONE : integer := ethernet_ii_out'low - 2; - signal sel : integer range SEL_ETH_NONE to ethernet_ii_out'high; - signal mac_destination_matches : std_logic; - signal rx_mac_header_rcv_delayed : std_logic; + constant SEL_ETH_I : integer := ethernet_ii_out'low - 1; + constant SEL_ETH_NONE : integer := ethernet_ii_out'low - 2; + signal sel : integer range SEL_ETH_NONE to ethernet_ii_out'high; + signal mac_destination_matches : std_logic; + signal rx_mac_header_rcv_delayed : std_logic; begin mac_destination_matches <= '1' when -- @@ -112,10 +112,10 @@ begin end block rx; tx : block - type state_t is (IDLE, TXD); - signal state : state_t; + type state_t is (IDLE, TXD); + signal state : state_t; constant SEL_ETH_I : integer := ethernet_ii_out'low - 1; - signal sel : integer range SEL_ETH_I to ethernet_ii_in'high; + signal sel : integer range SEL_ETH_I to ethernet_ii_in'high; begin arb : process(clk, rst) is begin diff --git a/trashernet/trashernet_icmp.vhd b/trashernet/trashernet_icmp.vhd index 4be3bdd..be883d4 100644 --- a/trashernet/trashernet_icmp.vhd +++ b/trashernet/trashernet_icmp.vhd @@ -56,13 +56,13 @@ begin ); rx : block - signal sr : byte_vector(0 to 3); - alias sr_type is sr(0); - alias sr_code is sr(1); - alias sr_checksum is sr(2 to 3); + signal sr : byte_vector(0 to 3); + alias sr_type is sr(0); + alias sr_code is sr(1); + alias sr_checksum is sr(2 to 3); - type state_t is (HEADER, DATA, IGNORE); - signal state : state_t; + type state_t is (HEADER, DATA, IGNORE); + signal state : state_t; signal byte_count : integer range 0 to sr'length; @@ -117,8 +117,8 @@ begin signal checksum : unsigned(16 downto 0); signal checksum_ones : unsigned(15 downto 0); - type state_t is (IDLE, HEADER, PAYLOAD); - signal state : state_t; + type state_t is (IDLE, HEADER, PAYLOAD); + signal state : state_t; signal sr : byte_vector(0 to 3); signal byte_count : integer range 0 to sr'subtype'high; diff --git a/trashernet/trashernet_ipv4.vhd b/trashernet/trashernet_ipv4.vhd index fd29213..3760a38 100644 --- a/trashernet/trashernet_ipv4.vhd +++ b/trashernet/trashernet_ipv4.vhd @@ -44,27 +44,27 @@ begin constant BYTECOUNT_HEADER : integer := 20; -- Mandatory header fields signal sr : byte_vector(0 to BYTECOUNT_HEADER - 1) := (others => x"00"); -- Init to zero to squelch metavalue warnings - alias sr_version is sr(0)(7 downto 4); - alias sr_ihl is sr(0)(3 downto 0); - alias sr_dscp is sr(1)(7 downto 2); - alias sr_ecn is sr(1)(1 downto 0); - alias sr_total_length is sr(2 to 3); - alias sr_identification is sr(4 to 5); - alias sr_flags is sr(6)(7 downto 5); + alias sr_version is sr(0)(7 downto 4); + alias sr_ihl is sr(0)(3 downto 0); + alias sr_dscp is sr(1)(7 downto 2); + alias sr_ecn is sr(1)(1 downto 0); + alias sr_total_length is sr(2 to 3); + alias sr_identification is sr(4 to 5); + alias sr_flags is sr(6)(7 downto 5); signal sr_fragment_offset : std_logic_vector(12 downto 0); - alias sr_ttl is sr(8); - alias sr_protocol is sr(9); - alias sr_header_cks is sr(10 to 11); - alias sr_source_ip is sr(12 to 15); - alias sr_destination_ip is sr(16 to 19); + alias sr_ttl is sr(8); + alias sr_protocol is sr(9); + alias sr_header_cks is sr(10 to 11); + alias sr_source_ip is sr(12 to 15); + alias sr_destination_ip is sr(16 to 19); signal header_ok : std_logic; signal bytecount : integer range 0 to 65535; signal block_done : std_logic; - type state_t is (HEADER, OPT, PAYLOAD, DONE); - signal state : state_t; + type state_t is (HEADER, OPT, PAYLOAD, DONE); + signal state : state_t; begin sr_fragment_offset <= sr(6)(4 downto 0) & sr(7); @@ -138,8 +138,8 @@ begin end block rx; tx : block - type state_t is (IDLE, ARP, CALC_CKS, HEADER, PAYLOAD); - signal state : state_t; + type state_t is (IDLE, ARP, CALC_CKS, HEADER, PAYLOAD); + signal state : state_t; signal full_length : ipv4_length; diff --git a/trashernet/trashernet_ipv4prot.vhd b/trashernet/trashernet_ipv4prot.vhd index e150199..77c2a30 100644 --- a/trashernet/trashernet_ipv4prot.vhd +++ b/trashernet/trashernet_ipv4prot.vhd @@ -83,8 +83,8 @@ begin end block rx; tx : block - type state_t is (IDLE, TXD); - signal state : state_t; + type state_t is (IDLE, TXD); + signal state : state_t; begin arb : process(clk, rst) is diff --git a/trashernet/trashernet_mac.vhd b/trashernet/trashernet_mac.vhd index 72494d3..9e1ee93 100644 --- a/trashernet/trashernet_mac.vhd +++ b/trashernet/trashernet_mac.vhd @@ -41,10 +41,10 @@ begin constant HEAD_LENGTH : integer := mac_out.rx_header.mac_destination'length + mac_out.rx_header.mac_source'length + mac_out.rx_header.mac_ethertype'length; constant CRC_LENGTH : integer := 4; - signal state : state_t; - signal sr_head : byte_vector(0 to HEAD_LENGTH - 1); + signal state : state_t; + signal sr_head : byte_vector(0 to HEAD_LENGTH - 1); constant BYTE_COUNT_MAX : integer := maximum(HEAD_LENGTH, CRC_LENGTH) - 1; - signal byte_count : integer range 0 to BYTE_COUNT_MAX; + signal byte_count : integer range 0 to BYTE_COUNT_MAX; signal sr_payload : byte_vector(0 to 4); @@ -102,7 +102,7 @@ begin byte_count <= byte_count + 1; end if; end if; - when PAYLOAD => -- @suppress "Dead state 'PAYLOAD'": Outgoing transition provided outside of case statement (RX disabled or error) + when PAYLOAD => -- @suppress "Dead state 'PAYLOAD'": Outgoing transition provided outside of case statement (RX disabled or error) if phy_out.rx_data_valid then sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data; if byte_count = CRC_LENGTH then @@ -136,14 +136,14 @@ begin end block rx; tx : block - type tx_state_t is (IDLE, HEADER, DATA, PAD, TXCRC); - signal tx_state : tx_state_t; + type tx_state_t is (IDLE, HEADER, DATA, PAD, TXCRC); + signal tx_state : tx_state_t; - signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1); + signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1); constant SR_CNT_MAX : integer := sr'high; - signal sr_cnt : integer range 0 to SR_CNT_MAX; + signal sr_cnt : integer range 0 to SR_CNT_MAX; constant BYTE_CNT_MAX : integer := ETH_FRAME_MIN_LENGTH - 4; -- Minus four because the CRC is *after* the PAD - signal byte_cnt : integer range 0 to BYTE_CNT_MAX; + signal byte_cnt : integer range 0 to BYTE_CNT_MAX; signal crc : std_logic_vector(ETH_POLYNOMIAL'range); signal crc_clear : std_logic; diff --git a/trashernet/trashernet_phy.vhd b/trashernet/trashernet_phy.vhd index 597458c..9024aa8 100644 --- a/trashernet/trashernet_phy.vhd +++ b/trashernet/trashernet_phy.vhd @@ -44,7 +44,7 @@ begin common : block constant TICK_MS_CNT_MAX : integer := (F_CLK / 1000) - 1; - signal tick_ms_count : integer range 0 to TICK_MS_CNT_MAX; + signal tick_ms_count : integer range 0 to TICK_MS_CNT_MAX; begin mstick : process(clk, rst) is begin @@ -80,7 +80,7 @@ begin -- NLP supervision constant NLP_TIMEOUT_CNT_MAX : integer := (16 + 8) - 1; -- Every 16 ms (timebase 1 ms) - signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX; + signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX; begin -- Synchronize RX input synchronizer_rxp_inst : entity work.synchronizer @@ -111,26 +111,26 @@ begin demanchestizer : block -- Transition detector - constant BIT_LENGTH_LONG : integer := F_CLK / F_ETH - 1; - constant BIT_LENGTH_SHORT : integer := F_CLK / (F_ETH * 2) - 1; - constant BIT_LENGTH_TOLERANCE : integer := (F_CLK / F_ETH) / 5; - constant BIT_LENGTH_TIMEOUT : integer := BIT_LENGTH_LONG + BIT_LENGTH_TOLERANCE + 1; - signal sample_count : integer range 0 to BIT_LENGTH_TIMEOUT; - type transition_duration_t is (SHORT, LONG); - signal transition_duration : transition_duration_t; - signal transition_stb : std_logic; - signal transition_activity : std_logic; + constant BIT_LENGTH_LONG : integer := F_CLK / F_ETH - 1; + constant BIT_LENGTH_SHORT : integer := F_CLK / (F_ETH * 2) - 1; + constant BIT_LENGTH_TOLERANCE : integer := (F_CLK / F_ETH) / 5; + constant BIT_LENGTH_TIMEOUT : integer := BIT_LENGTH_LONG + BIT_LENGTH_TOLERANCE + 1; + signal sample_count : integer range 0 to BIT_LENGTH_TIMEOUT; + type transition_duration_t is (SHORT, LONG); + signal transition_duration : transition_duration_t; + signal transition_stb : std_logic; + signal transition_activity : std_logic; -- Transition analysis signal last_transition : transition_duration_t; - type bit_ev_t is (NONE, TOGGLE, KEEP, ERROR); + type bit_ev_t is (NONE, TOGGLE, KEEP, ERROR); signal bit_ev : bit_ev_t; -- Bit recovery - type demanchestization_state_t is (SYNC, DATA, ERROR); - signal demanchestization_state : demanchestization_state_t; + type demanchestization_state_t is (SYNC, DATA, ERROR); + signal demanchestization_state : demanchestization_state_t; constant DEMANCHESTIZATION_MIN_SYNC_CNT_MAX : integer := (4 * 8) - 1; -- 4 good sync bytes - signal demanchestization_min_sync_cnt : integer range 0 to DEMANCHESTIZATION_MIN_SYNC_CNT_MAX; + signal demanchestization_min_sync_cnt : integer range 0 to DEMANCHESTIZATION_MIN_SYNC_CNT_MAX; begin -- Detects spacing of transitions transition_detector : process(clk, rst) is @@ -253,7 +253,7 @@ begin begin if rst then phy_out.rx_data_valid <= '0'; - phy_out.rx_data <= (others => '0'); -- Needed for yosys to compile + phy_out.rx_data <= (others => '0'); -- Needed for yosys to compile elsif rising_edge(clk) then phy_out.rx_data_valid <= '0'; @@ -301,21 +301,21 @@ begin constant TX_STB_SKIP_ERROR : real := abs (round(TX_STB_CNT_IDEAL) - TX_STB_CNT_IDEAL); constant TX_STB_CNT_MAX : integer := integer(round(TX_STB_CNT_IDEAL + 0.25)) - 1; -- Round up starting for error > 0.25 constant TX_STB_SKIP_SECOND : boolean := TX_STB_SKIP_ERROR >= 0.25; -- Skip one clock cycle every other symbol to hit clock rate in between when the divider is close to x.5 - signal tx_stb_cnt : integer range 0 to TX_STB_CNT_MAX; + signal tx_stb_cnt : integer range 0 to TX_STB_CNT_MAX; - type tx_state_t is (IDLE, NLP, TX, IPG); - signal tx_state : tx_state_t; - signal sr : std_logic_vector(phy_in.tx_data'range); - signal bit_stage : std_logic; + type tx_state_t is (IDLE, NLP, TX, IPG); + signal tx_state : tx_state_t; + signal sr : std_logic_vector(phy_in.tx_data'range); + signal bit_stage : std_logic; constant BIT_CNT_MAX_IPG : integer := 96; constant BIT_CNT_MAX_DATA : integer := sr'length - 1; - signal bit_cnt : integer range 0 to maximum(BIT_CNT_MAX_IPG, BIT_CNT_MAX_DATA); + signal bit_cnt : integer range 0 to maximum(BIT_CNT_MAX_IPG, BIT_CNT_MAX_DATA); constant NLP_CNT_MAX : integer := 15; -- specced 16 ms, but there's margin, so let's choose 15 to save a bit (timebase 1 ms) - signal nlp_cnt : integer range 0 to NLP_CNT_MAX; + signal nlp_cnt : integer range 0 to NLP_CNT_MAX; - type tx_mode_t is (OFF, NLP, ACTIVE); - signal tx_mode : tx_mode_t; + type tx_mode_t is (OFF, NLP, ACTIVE); + signal tx_mode : tx_mode_t; begin tx_main : process(clk, rst) is procedure transmit_byte is diff --git a/trashernet/trashernet_pkg.vhd b/trashernet/trashernet_pkg.vhd index 3fba0b8..0dfd60c 100644 --- a/trashernet/trashernet_pkg.vhd +++ b/trashernet/trashernet_pkg.vhd @@ -14,14 +14,14 @@ use ieee.numeric_std.all; package trashernet_pkg is -- General types - subtype byte is std_logic_vector(7 downto 0); - type byte_vector is array (natural range <>) of byte; + subtype byte is std_logic_vector(7 downto 0); + type byte_vector is array (natural range <>) of byte; -- MAC specific types - subtype mac_addr_t is byte_vector(0 to 5); + subtype mac_addr_t is byte_vector(0 to 5); constant MAC_ADDR_BROADCAST : mac_addr_t := (others => x"FF"); function mac_to_string(constant mac_address : in mac_addr_t) return string; - subtype ethertype_t is byte_vector(0 to 1); + subtype ethertype_t is byte_vector(0 to 1); type mac_header_fields is record mac_destination : mac_addr_t; -- Destination MAC address @@ -80,13 +80,13 @@ package trashernet_pkg is end record mac_out_t; -- MAC ETH interface - type ethernet_ii_protocol_t is record + type ethernet_ii_protocol_t is record ethertype : ethertype_t; end record; - type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t; - constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- @suppress "Null range": We want a NULL vector here to remove the logic - constant ETHERNET_II_PROTOCOL_IPV4 : ethernet_ii_protocol_t := (ethertype => (x"08", x"00")); - constant ETHERNET_II_PROTOCOL_ARP : ethernet_ii_protocol_t := (ethertype => (x"08", x"06")); + type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t; + constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- @suppress "Null range": We want a NULL vector here to remove the logic + constant ETHERNET_II_PROTOCOL_IPV4 : ethernet_ii_protocol_t := (ethertype => (x"08", x"00")); + constant ETHERNET_II_PROTOCOL_ARP : ethernet_ii_protocol_t := (ethertype => (x"08", x"06")); type ethernet_i_out_t is record rx_mac_address : mac_addr_t; -- Source MAC address @@ -121,9 +121,9 @@ package trashernet_pkg is tx_data : byte; -- TX data tx_en : std_logic; -- Start and continue transmitting end record; - type ethernet_ii_out_vector is array (natural range <>) of ethernet_ii_out_t; - type ethernet_ii_in_vector is array (natural range <>) of ethernet_ii_in_t; - constant ETHERNET_II_IN_UNUSED : ethernet_ii_in_t := (tx_mac_address => (others => x"00"), tx_data => x"00", others => '0'); + type ethernet_ii_out_vector is array (natural range <>) of ethernet_ii_out_t; + type ethernet_ii_in_vector is array (natural range <>) of ethernet_ii_in_t; + constant ETHERNET_II_IN_UNUSED : ethernet_ii_in_t := (tx_mac_address => (others => x"00"), tx_data => x"00", others => '0'); -- ARP interface type arp_out_t is record @@ -137,12 +137,12 @@ package trashernet_pkg is end record arp_in_t; -- IPv4 interface - subtype ipv4_protocol is byte; - type ipv4_protocol_vector is array (natural range <>) of ipv4_protocol; - constant IPV4_PROTOCOL_ICMP : ipv4_protocol := x"01"; - constant IPV4_PROTOCOL_TCP : ipv4_protocol := x"06"; - constant IPV4_PROTOCOL_UDP : ipv4_protocol := x"11"; - subtype ipv4_length is unsigned(15 downto 0); + subtype ipv4_protocol is byte; + type ipv4_protocol_vector is array (natural range <>) of ipv4_protocol; + constant IPV4_PROTOCOL_ICMP : ipv4_protocol := x"01"; + constant IPV4_PROTOCOL_TCP : ipv4_protocol := x"06"; + constant IPV4_PROTOCOL_UDP : ipv4_protocol := x"11"; + subtype ipv4_length is unsigned(15 downto 0); type ipv4_out_t is record rx_ip_address : ip_addr_t; -- Source IP address @@ -189,12 +189,12 @@ package trashernet_pkg is tx_en : std_logic; -- Start and continue transmitting end record ipv4_protocol_in_t; type ipv4_protocol_out_vector is array (natural range <>) of ipv4_protocol_out_t; - type ipv4_protocol_in_vector is array (natural range <>) of ipv4_protocol_in_t; + type ipv4_protocol_in_vector is array (natural range <>) of ipv4_protocol_in_t; -- UDP interface - subtype udp_port_t is unsigned(15 downto 0); + subtype udp_port_t is unsigned(15 downto 0); subtype udp_length_t is unsigned(15 downto 0); - type udp_out_t is record + type udp_out_t is record rx_data : byte; -- RX Data rx_data_valid : std_logic; -- RX data valid strobe @@ -220,20 +220,20 @@ package trashernet_pkg is tx_data : byte; end record udp_in_t; - type udpprot_rx_out_t is record + type udpprot_rx_out_t is record temp : std_logic; end record udpprot_rx_out_t; - type udpprot_rx_in_t is record + type udpprot_rx_in_t is record temp : std_logic; end record udpprot_rx_in_t; - type udpprot_tx_out_t is record + type udpprot_tx_out_t is record temp : std_logic; end record udpprot_tx_out_t; - type udpprot_tx_in_t is record + type udpprot_tx_in_t is record temp : std_logic; end record udpprot_tx_in_t; - subtype portnum is integer range 0 to 65535; - type udp_port_vector is array (natural range <>) of portnum; + subtype portnum is integer range 0 to 65535; + type udp_port_vector is array (natural range <>) of portnum; -- General helper functions function to_std_logic(constant bool : boolean) return std_logic;