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Author SHA1 Message Date
Markus Koch 5b54a596c1 doc: Add circuit diagram 2022-01-30 19:29:09 +01:00
Markus Koch 61812c133f phy: Improve header synchronization 2022-01-30 19:26:43 +01:00
3 changed files with 3067 additions and 12 deletions

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@ -17,10 +17,15 @@ When writing it, the following were the main design philosophies:
## Hardware
TBD. TL;DR:
![Circuit Diagram](doc/circuit.svg)
* RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL.
* TX: Meh, a series current limiting resistor is good enough.
* RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL. Also, pull up/down resistors help to avoid glitchy behavior with no cable connected or little data activity.
* TX: Meh, a series current limiting resistor is good enough. Drive two outputs differentially to increase the voltage swing. (Technically not true antivalent signals as there's also the "off" state with both disabled.)
Notes:
* The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
* On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D
## License

3039
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@ -128,7 +128,9 @@ begin
-- Bit recovery
type demanchestization_state_t is (SYNC, DATA, ERROR);
signal demanchestization_state : demanchestization_state_t;
signal demanchestization_state : demanchestization_state_t;
constant DEMANCHESTIZATION_MIN_SYNC_CNT_MAX : integer := (4 * 8) - 1; -- 4 good sync bytes
signal demanchestization_min_sync_cnt : integer range 0 to DEMANCHESTIZATION_MIN_SYNC_CNT_MAX;
begin
-- Detects spacing of transitions
transition_detector : process(clk, rst) is
@ -200,21 +202,30 @@ begin
bit_recovery : process(clk, rst) is
begin
if rst then
demanchestization_state <= SYNC;
bit_stb <= '0';
phy_out.rx_active <= '0';
phy_out.rx_error <= '0';
demanchestization_state <= SYNC;
bit_stb <= '0';
phy_out.rx_active <= '0';
phy_out.rx_error <= '0';
demanchestization_min_sync_cnt <= DEMANCHESTIZATION_MIN_SYNC_CNT_MAX;
elsif rising_edge(clk) then
bit_stb <= '0';
phy_out.rx_error <= '0';
if (bit_ev = TOGGLE) and (demanchestization_min_sync_cnt /= 0) then
demanchestization_min_sync_cnt <= demanchestization_min_sync_cnt - 1;
elsif (bit_ev = KEEP) or (bit_ev = ERROR) then
demanchestization_min_sync_cnt <= DEMANCHESTIZATION_MIN_SYNC_CNT_MAX;
end if;
if (bit_ev /= NONE) then
case demanchestization_state is
when SYNC =>
if (bit_ev = KEEP) then
bit_value <= '1';
demanchestization_state <= DATA;
phy_out.rx_active <= '1';
if demanchestization_min_sync_cnt = 0 then
bit_value <= '1';
demanchestization_state <= DATA;
phy_out.rx_active <= '1';
end if;
end if;
when DATA => -- @suppress: Condition outside of case allows to exit this state
bit_value <= not bit_value when bit_ev = TOGGLE else bit_value;
@ -225,7 +236,7 @@ begin
end if;
if (bit_ev = ERROR) then
phy_out.rx_error <= '1';
phy_out.rx_error <= '1' when (demanchestization_state = DATA) else '0';
demanchestization_state <= ERROR;
end if;