fpga/trashernet
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base: fpga:3240f363baf412617c0118292abd98df91a0cbb1
Branches Tags
fpga:master
fpga:feature/trashernet-soc
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1
..
compare: fpga:651b6bb11e07eeeae43f1050c87ab6ca9241bca3
Branches Tags
fpga:feature/trashernet-soc
fpga:master
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1

No commits in common. "3240f363baf412617c0118292abd98df91a0cbb1" and "651b6bb11e07eeeae43f1050c87ab6ca9241bca3" have entirely different histories.
3240f363ba ... 651b6bb11e

2 changed files with 13 additions and 41 deletions
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4
design/top_hwitl.vhd
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@ -215,13 +215,9 @@ architecture eth of top_hwitl is
signal arp_in : arp_in_t; signal arp_in : arp_in_t;
begin begin
trashernet_arp_inst : entity trashernet.trashernet_arp trashernet_arp_inst : entity trashernet.trashernet_arp
generic map(
TIMEOUT_TICK_FREQ => F_CLK
)
port map( port map(
clk => clk, clk => clk,
rst => rst, rst => rst,
timeout_tick => '1',
mac_config => ETH_CONFIG, mac_config => ETH_CONFIG,
ip_config => IP_CONFIG, ip_config => IP_CONFIG,
arp_out => arp_out, arp_out => arp_out,

50
trashernet/trashernet_arp.vhd
View File

@ -16,14 +16,10 @@ use ieee.numeric_std.all;
use work.trashernet_pkg.all; use work.trashernet_pkg.all;
entity trashernet_arp is entity trashernet_arp is
generic(
TIMEOUT_TICK_FREQ : integer
);
port( port(
-- Global -- Global
clk : in std_logic; -- Global clock clk : in std_logic; -- Global clock
rst : in std_logic; -- Asynchronous reset rst : in std_logic; -- Asynchronous reset
timeout_tick : in std_logic; -- Global timeout tick strobe
-- Configuration -- Configuration
mac_config : in configuration_t; -- Trashernet MAC configuration mac_config : in configuration_t; -- Trashernet MAC configuration
@ -47,8 +43,6 @@ architecture rtl of trashernet_arp is
constant OPER_REQUEST : byte_vector := (x"00", x"01"); constant OPER_REQUEST : byte_vector := (x"00", x"01");
constant OPER_REPLY : byte_vector := (x"00", x"02"); constant OPER_REPLY : byte_vector := (x"00", x"02");
constant ARP_TIMEOUT : time := 1 sec;
signal arp_tx_reply_rq : std_logic; -- Request to transmit an ARP reply signal arp_tx_reply_rq : std_logic; -- Request to transmit an ARP reply
signal arp_tx_reply_tha : mac_addr_t; -- Target MAC to use in reply (SHA in received packet) signal arp_tx_reply_tha : mac_addr_t; -- Target MAC to use in reply (SHA in received packet)
signal arp_tx_reply_tpa : ip_addr_t; -- Target IP to use in reply (SPA in received packet) signal arp_tx_reply_tpa : ip_addr_t; -- Target IP to use in reply (SPA in received packet)
@ -61,7 +55,6 @@ architecture rtl of trashernet_arp is
signal arp_rx_reply_stb : std_logic; -- An ARP reply was received (strobe) signal arp_rx_reply_stb : std_logic; -- An ARP reply was received (strobe)
signal arp_rx_sha : mac_addr_t; -- The MAC address of the reply sender, valid with arp_rx_reply signal arp_rx_sha : mac_addr_t; -- The MAC address of the reply sender, valid with arp_rx_reply
signal arp_rx_spa : ip_addr_t; -- The IP address of the reply sender, valid with arp_rx_reply signal arp_rx_spa : ip_addr_t; -- The IP address of the reply sender, valid with arp_rx_reply
begin begin
resolver : block resolver : block
type resolver_state_t is (IDLE, QUERY_MAC); type resolver_state_t is (IDLE, QUERY_MAC);
@ -81,7 +74,7 @@ begin
replied_ip <= (others => x"00"); -- 0.0.0.0 replied_ip <= (others => x"00"); -- 0.0.0.0
arp_out.arp_ok_stb <= '0'; arp_out.arp_ok_stb <= '0';
arp_out.arp_fail_stb <= '0'; arp_out.arp_fail_stb <= '0';
arp_tx_request_rq <= '0'; arp_tx_request_rq <= '0';
elsif rising_edge(clk) then elsif rising_edge(clk) then
arp_out.arp_ok_stb <= '0'; arp_out.arp_ok_stb <= '0';
@ -110,33 +103,16 @@ begin
arp_tx_request_rq <= '0'; arp_tx_request_rq <= '0';
end if; end if;
if query_mac_found or query_timeout then if query_mac_found or query_timeout then
arp_out.arp_ok_stb <= query_mac_found; arp_out.arp_ok_stb <= query_mac_found;
arp_out.arp_fail_stb <= not query_mac_found; arp_out.arp_fail_stb <= not query_mac_found;
state <= IDLE; state <= IDLE;
end if; end if;
end case; end case;
end if; end if;
end process arp_resolver_main; end process arp_resolver_main;
query_mac_found <= '1' when (arp_tx_request_tpa = replied_ip) else '0'; query_mac_found <= '1' when (arp_tx_request_tpa = replied_ip) else '0';
arp_out.arp_mac <= replied_mac; arp_out.arp_mac <= replied_mac;
arp_tx_request_tpa <= arp_in.arp_ip; arp_tx_request_tpa <= arp_in.arp_ip;
timeout_timer_inst : entity work.timer
generic map(
F_TICK => TIMEOUT_TICK_FREQ,
DURATION => ARP_TIMEOUT,
AUTOSTART => false
)
port map(
clk => clk,
rst => rst,
tick => timeout_tick,
start => arp_tx_request_rq,
expired => query_timeout,
expired_stb => open
);
end block resolver; end block resolver;
rx : block rx : block
@ -274,7 +250,7 @@ begin
tx_fsm : process(clk, rst) is tx_fsm : process(clk, rst) is
begin begin
if rst then if rst then
arp_tx_reply_ack <= '0'; arp_tx_reply_ack <= '0';
arp_tx_request_ack <= '0'; arp_tx_request_ack <= '0';
elsif rising_edge(clk) then elsif rising_edge(clk) then
@ -289,14 +265,14 @@ begin
case state is case state is
when IDLE => when IDLE =>
if arp_tx_reply_rq then if arp_tx_reply_rq then
state <= TRANSMIT; state <= TRANSMIT;
arp_tx_reply_ack <= '1'; arp_tx_reply_ack <= '1';
sr <= arp_reply_preload; sr <= arp_reply_preload;
ethernet_ii_in.tx_mac_address <= arp_tx_reply_tha; ethernet_ii_in.tx_mac_address <= arp_tx_reply_tha;
elsif arp_tx_request_rq then elsif arp_tx_request_rq then
state <= TRANSMIT; state <= TRANSMIT;
arp_tx_request_ack <= '1'; arp_tx_request_ack <= '1';
sr <= arp_request_preload; sr <= arp_request_preload;
ethernet_ii_in.tx_mac_address <= MAC_ADDR_BROADCAST; ethernet_ii_in.tx_mac_address <= MAC_ADDR_BROADCAST;
end if; end if;
@ -310,8 +286,8 @@ begin
end if; end if;
end process tx_fsm; end process tx_fsm;
ethernet_ii_in.tx_en <= '1' when state = TRANSMIT else '0'; ethernet_ii_in.tx_en <= '1' when state = TRANSMIT else '0';
ethernet_ii_in.tx_data <= sr(0); ethernet_ii_in.tx_data <= sr(0);
end block tx; end block tx;
end architecture rtl; end architecture rtl;