fpga/trashernet
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base: fpga:35093bba85292d6b0b10ef754122129ec8253675
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fpga:master
fpga:feature/trashernet-soc
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1
...
compare: fpga:1bff61d24a68e29359b32ee533ec446d40ee7f97
Branches Tags
fpga:feature/trashernet-soc
fpga:master
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1

2 Commits
35093bba85 ... 1bff61d24a

Author SHA1 Message Date
Markus Koch
1bff61d24a Fix code formatting 2021-09-04 19:33:44 +02:00
Markus Koch
743d2465d9 Add license headers 2021-09-04 19:33:32 +02:00
11 changed files with 120 additions and 5 deletions
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16
bench/bench_crc.vhd
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@ -1,3 +1,13 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- bench_crc.vhd : Stimulus-only test bench for the CRC
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
@ -18,9 +28,9 @@ architecture bench of bench_crc is
begin begin
crc_inst : entity trashernet.crc crc_inst : entity trashernet.crc
generic map( generic map(
POLYNOMIAL => POLYNOMIAL, POLYNOMIAL => POLYNOMIAL,
START => x"FFFFFFFF", START => x"FFFFFFFF",
FINAL_XOR => x"FFFFFFFF", FINAL_XOR => x"FFFFFFFF",
REVERSE_OUT => true REVERSE_OUT => true
) )
port map( port map(

10
bench/bench_pkg.vhd
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@ -1,3 +1,13 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- bench_pkg.vhd : Types and functions used for the benches
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;

11
bench/bench_trashernet_mac.vhd
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@ -1,3 +1,14 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- bench_trashernet_mac.vhd : Stimulus-only test bench for the MAC+PHY parts
-- Tests TX path through the RX path. Not great, but whatever.
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

11
bench/bench_trashernet_phy.vhd
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@ -1,3 +1,14 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- bench_trashernet_phy.vhd : Stimulus-only test bench for the PHY part
-- Tests only the RX path.
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

10
trashernet/cdc_strobe.vhd
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@ -1,3 +1,13 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- cdc_strobe.vhd : CDC for strobe-signals
-- Make sure to leave enough(TM) time between strobes.
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

10
trashernet/crc.vhd
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@ -1,3 +1,13 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- crc.vhd : Generic CRC implementation
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

10
trashernet/synchronizer.vhd
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@ -1,3 +1,13 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- synchronizer.vhd : Basic shift-register based synchronizer
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

11
trashernet/trashernet_mac.vhd
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@ -1,3 +1,14 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- trashernet_mac.vhd : Ethernet OSI Layer 2, Data Link
-- Implements packet handling and MAC-Layer en/decoding.
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

11
trashernet/trashernet_phy.vhd
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@ -1,3 +1,14 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- trashernet_phy.vhd : Ethernet OSI Layer 1, Physical
-- Implements low-level bit encoding and timing and frame synchronization.
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;

15
trashernet/trashernet_phy_cdc.vhd
View File

@ -1,3 +1,14 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- trashernet_phy_cdc.vhd : Dual clock wrapper for the trashernet_phy
-- Implements CDC between the PHY and DATA clock domains.
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
@ -16,11 +27,11 @@ entity trashernet_phy_cdc is
rst : in std_logic; -- Asynchronous reset rst : in std_logic; -- Asynchronous reset
-- System interface -- System interface
rx_data : out byte; -- RX Data rx_data : out byte; -- RX Data
rx_data_valid : out std_logic; -- RX Data valid rx_data_valid : out std_logic; -- RX Data valid
rx_active : out std_logic; -- RX of packet in progress rx_active : out std_logic; -- RX of packet in progress
tx_data : in byte; -- TX Data tx_data : in byte; -- TX Data
tx_data_en : in std_logic; -- Transmitter enable tx_data_en : in std_logic; -- Transmitter enable
tx_data_ack : out std_logic; -- Latched data_tx tx_data_ack : out std_logic; -- Latched data_tx
tx_active : out std_logic; -- Transmission in progress tx_active : out std_logic; -- Transmission in progress

10
trashernet/trashernet_types.vhd
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@ -1,3 +1,13 @@
-- -------------------------------------------------------------------------- --
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
-- -------------------------------------------------------------------------- --
-- trashernet_types.vhd : VHDL types used throughout Trashernet
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;