fpga/trashernet
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base: fpga:5b54a596c19a64c314a2024ae3dcb932889d09a3
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fpga:master
fpga:feature/trashernet-soc
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1
..
compare: fpga:075f935e12dd7d20fe7b20331bc3bef2e10e435f
Branches Tags
fpga:feature/trashernet-soc
fpga:master
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1

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11
README.MD
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@ -17,15 +17,10 @@ When writing it, the following were the main design philosophies:
## Hardware
![Circuit Diagram](doc/circuit.svg)
TBD. TL;DR:
* RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL. Also, pull up/down resistors help to avoid glitchy behavior with no cable connected or little data activity.
* TX: Meh, a series current limiting resistor is good enough. Drive two outputs differentially to increase the voltage swing. (Technically not true antivalent signals as there's also the "off" state with both disabled.)
Notes:
* The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
* On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D
* RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL.
* TX: Meh, a series current limiting resistor is good enough.
## License

3039
doc/circuit.svg
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13
trashernet/trashernet_phy.vhd
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@ -129,8 +129,6 @@ begin
-- Bit recovery
type demanchestization_state_t is (SYNC, DATA, ERROR);
signal demanchestization_state : demanchestization_state_t;
constant DEMANCHESTIZATION_MIN_SYNC_CNT_MAX : integer := (4 * 8) - 1; -- 4 good sync bytes
signal demanchestization_min_sync_cnt : integer range 0 to DEMANCHESTIZATION_MIN_SYNC_CNT_MAX;
begin
-- Detects spacing of transitions
transition_detector : process(clk, rst) is
@ -206,27 +204,18 @@ begin
bit_stb <= '0';
phy_out.rx_active <= '0';
phy_out.rx_error <= '0';
demanchestization_min_sync_cnt <= DEMANCHESTIZATION_MIN_SYNC_CNT_MAX;
elsif rising_edge(clk) then
bit_stb <= '0';
phy_out.rx_error <= '0';
if (bit_ev = TOGGLE) and (demanchestization_min_sync_cnt /= 0) then
demanchestization_min_sync_cnt <= demanchestization_min_sync_cnt - 1;
elsif (bit_ev = KEEP) or (bit_ev = ERROR) then
demanchestization_min_sync_cnt <= DEMANCHESTIZATION_MIN_SYNC_CNT_MAX;
end if;
if (bit_ev /= NONE) then
case demanchestization_state is
when SYNC =>
if (bit_ev = KEEP) then
if demanchestization_min_sync_cnt = 0 then
bit_value <= '1';
demanchestization_state <= DATA;
phy_out.rx_active <= '1';
end if;
end if;
when DATA => -- @suppress: Condition outside of case allows to exit this state
bit_value <= not bit_value when bit_ev = TOGGLE else bit_value;
bit_stb <= '1';
@ -236,7 +225,7 @@ begin
end if;
if (bit_ev = ERROR) then
phy_out.rx_error <= '1' when (demanchestization_state = DATA) else '0';
phy_out.rx_error <= '1';
demanchestization_state <= ERROR;
end if;