⚠️ ETH and IPv4prot muxing fails when two access in the same cycle #13

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opened 2022-10-31 16:51:36 +01:00 by markus · 0 comments

Two sources: HIGH-prio and LOW-prio. Current selection is LOW-prio.

Both request at the same time.

Data and tx_en from LOW-prio is latched -> first word is taken from there. Now, arbitration does its job and switches to high prio. All acks and data go here.

--> First byte is from LOW-prio source, rest is from HIGH-prio.

Two sources: HIGH-prio and LOW-prio. Current selection is LOW-prio. Both request at the same time. Data and tx_en from LOW-prio is latched -> first word is taken from there. Now, arbitration does its job and switches to high prio. All acks and data go here. --> First byte is from LOW-prio source, rest is from HIGH-prio.
markus added this to the TCP <-> Serial Bridge milestone 2022-10-31 16:51:36 +01:00
markus added the
bug
label 2022-10-31 16:51:36 +01:00
markus changed title from ETH and IPv4prot muxing fails when two access in the same cycle to ⚠️ ETH and IPv4prot muxing fails when two access in the same cycle 2022-10-31 16:52:01 +01:00
markus modified the milestone from TCP <-> Serial Bridge to UDP <-> Serial Bridge 2023-01-21 20:27:47 +01:00
markus self-assigned this 2023-01-21 20:31:20 +01:00
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Reference: fpga/trashernet#13
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