-- -------------------------------------------------------------------------- -- -- TRASHERNET - A Trashy Ethernet Stack for FPGAs -- -- -------------------------------------------------------------------------- -- -- pll0.vhd : Simulates the PLL component present in some demo designs -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity pll0 is port( CLK : in std_logic; CLKOP : out std_logic; LOCK : out std_logic ); end entity pll0; architecture bench of pll0 is begin clock_driver : process constant period : time := 7.1429 ns; -- 140 MHz configured clock begin CLKOP <= '0'; LOCK <= '0'; wait until CLK'event; wait for 12 ns; LOCK <= '1'; loop CLKOP <= '0'; wait for period / 2; CLKOP <= '1'; wait for period / 2; end loop; end process clock_driver; end architecture bench;