-- -------------------------------------------------------------------------- -- -- TRASHERNET - A Trashy Ethernet Stack for FPGAs -- -- -------------------------------------------------------------------------- -- -- ledcon.vhd : Simple debug LED helper -- To blink or not blink. -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity ledcon is generic( F_CLK : integer; BLINK : boolean_vector ); port( clk : in std_logic; rst : in std_logic; sig : in std_logic_vector; led_n : out std_logic_vector ); end entity ledcon; architecture RTL of ledcon is constant MS_CNT_MAX : integer := integer(round(real(F_CLK) * (1.0 * 10.0 ** (-3)))); signal ms_cnt : integer range 0 to MS_CNT_MAX; signal ms_tick : std_logic; begin mstimer : process(clk, rst) is begin if rst then ms_cnt <= MS_CNT_MAX; elsif rising_edge(clk) then if (ms_cnt = 0) then ms_cnt <= MS_CNT_MAX; else ms_cnt <= ms_cnt - 1; end if; end if; end process mstimer; ms_tick <= '1' when ms_cnt = 0 else '0'; ledcongen : for i in sig'low to sig'high generate ledblock : block constant LED_CNT_MAX : integer := 50; -- on time, in ms constant LED_CNT_MIN : integer := -50; -- off time, in ms signal led_cnt : integer range LED_CNT_MIN to LED_CNT_MAX; begin ledgen : if BLINK(i) generate ledproc : process(clk, rst) is begin if rst then led_cnt <= LED_CNT_MIN; elsif rising_edge(clk) then if (led_cnt = LED_CNT_MIN) then if sig(i) then led_cnt <= LED_CNT_MAX; end if; elsif ms_tick then led_cnt <= led_cnt - 1; end if; end if; end process ledproc; led_n(i) <= '0' when led_cnt > 0 else '1'; else generate led_n(i) <= not sig(i); end generate ledgen; end block ledblock; end generate ledcongen; end architecture RTL;