-- -------------------------------------------------------------------------- -- -- TRASHERNET - A Trashy Ethernet Stack for FPGAs -- -- -------------------------------------------------------------------------- -- -- cdc_strobe.vhd : CDC for strobe-signals -- Make sure to leave enough(TM) time between strobes. -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cdc_strobe is generic( SYNCHRONIZERS : integer := 3 ); port( a_clk : in std_logic; a_rst : in std_logic; a_in : in std_logic; b_clk : in std_logic; b_rst : in std_logic; b_out : out std_logic ); end entity cdc_strobe; architecture rtl of cdc_strobe is signal a_toggle : std_logic; signal b_toggle : std_logic; signal b_toggle_last : std_logic; begin togglify : process(a_clk, a_rst) is begin if a_rst then a_toggle <= '0'; elsif rising_edge(a_clk) then if (a_in) then a_toggle <= not a_toggle; end if; end if; end process togglify; synchronizer_inst : entity work.synchronizer generic map( SIZE => SYNCHRONIZERS ) port map( clk => b_clk, rst => b_rst, data_in => a_toggle, data_out => b_toggle ); -- strobify b_toggle_last <= '0' when b_rst else b_toggle when rising_edge(b_clk); b_out <= (b_toggle ?/= b_toggle_last); end architecture rtl;