-- -------------------------------------------------------------------------- -- -- TRASHERNET - A Trashy Ethernet Stack for FPGAs -- -- -------------------------------------------------------------------------- -- -- trashernet_mac.vhd : Ethernet OSI Layer 2, Data Link -- Implements packet handling and MAC-Layer en/decoding. -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.trashernet_pkg.all; entity trashernet_mac is port( -- Global clk : in std_logic; -- Global clock rst : in std_logic; -- Asynchronous reset -- PHY signals phy_out : in phy_out_t; -- PHY application IF (out of PHY) phy_in : out phy_in_t; -- PHY application IF (into PHY) -- MAC application IF mac_out : out mac_out_t; -- MAC application IF (out of MAC) mac_in : in mac_in_t -- MAC application IF (into MAC) ); end entity trashernet_mac; architecture rtl of trashernet_mac is constant ETH_POLYNOMIAL : std_logic_vector(31 downto 0) := x"04C11DB7"; constant ETH_FRAME_MIN_LENGTH : integer := 64; begin rx : block type state_t is (HEAD, PAYLOAD); constant HEAD_LENGTH : integer := mac_out.rx_header.mac_destination'length + mac_out.rx_header.mac_source'length + mac_out.rx_header.mac_ethertype'length; constant CRC_LENGTH : integer := 4; signal state : state_t; signal sr_head : byte_vector(0 to HEAD_LENGTH - 1); constant BYTE_COUNT_MAX : integer := maximum(HEAD_LENGTH, CRC_LENGTH) - 1; signal byte_count : integer range 0 to BYTE_COUNT_MAX; signal sr_payload : byte_vector(0 to 4); signal crc : std_logic_vector(ETH_POLYNOMIAL'range); signal crc_ok : std_logic; signal crc_clear : std_logic; begin crc_inst : entity work.crc generic map( POLYNOMIAL => ETH_POLYNOMIAL, START => x"FFFFFFFF", FINAL_XOR => x"FFFFFFFF", REVERSE_OUT => true ) port map( clk => clk, rst => rst, data => phy_out.rx_data, data_valid => phy_out.rx_data_valid, crc_clear => crc_clear, crc_out => crc ); crc_ok <= '1' when crc = x"2144DF1C" else '0'; main : process(clk, rst) is begin if rst then byte_count <= 0; mac_out.rx_mac_valid <= '0'; mac_out.rx_mac_crc_error <= '0'; mac_out.rx_mac_crc_ok <= '0'; mac_out.rx_mac_header_rcv <= '0'; crc_clear <= '0'; state <= HEAD; elsif rising_edge(clk) then mac_out.rx_mac_valid <= '0'; mac_out.rx_mac_crc_error <= '0'; mac_out.rx_mac_crc_ok <= '0'; mac_out.rx_mac_header_rcv <= '0'; crc_clear <= '0'; case state is when HEAD => if phy_out.rx_data_valid then sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & phy_out.rx_data; if byte_count = (HEAD_LENGTH - 1) then state <= PAYLOAD; byte_count <= 0; mac_out.rx_mac_header_rcv <= '1'; end if; if (byte_count /= BYTE_COUNT_MAX) then byte_count <= byte_count + 1; end if; end if; when PAYLOAD => -- @suppress "Dead state 'PAYLOAD'": Outgoing transition provided outside of case statement (RX disabled or error) if phy_out.rx_data_valid then sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & phy_out.rx_data; if byte_count = CRC_LENGTH then mac_out.rx_mac_valid <= '1'; else byte_count <= byte_count + 1; end if; end if; if not phy_out.rx_active then mac_out.rx_mac_crc_ok <= crc_ok; mac_out.rx_mac_crc_error <= not crc_ok; end if; if phy_out.rx_error then mac_out.rx_mac_crc_error <= '1'; end if; end case; if (not phy_out.rx_active) or phy_out.rx_error then byte_count <= 0; state <= HEAD; crc_clear <= '1'; end if; end if; end process main; mac_out.rx_header.mac_destination <= sr_head(0 to 5); mac_out.rx_header.mac_source <= sr_head(6 to 11); mac_out.rx_header.mac_ethertype <= sr_head(12 to 13); mac_out.rx_mac_data <= sr_payload(0); end block rx; tx : block type tx_state_t is (IDLE, HEADER, DATA, PAD, TXCRC); signal tx_state : tx_state_t; signal sr : byte_vector(0 to mac_in.tx_header.mac_destination'length + mac_in.tx_header.mac_source'length + mac_in.tx_header.mac_ethertype'length - 1); constant SR_CNT_MAX : integer := sr'high; signal sr_cnt : integer range 0 to SR_CNT_MAX; constant BYTE_CNT_MAX : integer := ETH_FRAME_MIN_LENGTH - 4; -- Minus four because the CRC is *after* the PAD signal byte_cnt : integer range 0 to BYTE_CNT_MAX; signal crc : std_logic_vector(ETH_POLYNOMIAL'range); signal crc_clear : std_logic; signal crc_valid : std_logic; begin crc_inst : entity work.crc generic map( POLYNOMIAL => ETH_POLYNOMIAL, START => x"FFFFFFFF", FINAL_XOR => x"FFFFFFFF", REVERSE_OUT => true ) port map( clk => clk, rst => rst, data => phy_in.tx_data, data_valid => crc_valid, crc_clear => crc_clear, crc_out => crc ); tx_main : process(clk, rst) is variable more_data : std_logic; begin if rst then mac_out.tx_mac_data_ack <= '0'; tx_state <= IDLE; sr_cnt <= 0; byte_cnt <= 0; elsif rising_edge(clk) then mac_out.tx_mac_data_ack <= '0'; crc_valid <= '0'; more_data := more_data and mac_in.tx_mac_data_en; -- Latch a short low-pulse on tx_en if phy_out.tx_data_ack then sr <= sr(sr'low + 1 to sr'high) & x"00"; crc_valid <= '1'; if sr_cnt /= 0 then sr_cnt <= sr_cnt - 1; end if; if byte_cnt /= 0 then byte_cnt <= byte_cnt - 1; end if; end if; case tx_state is when IDLE => -- Idle + prepare sync header if not phy_out.tx_active and mac_in.tx_mac_data_en then more_data := '1'; sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5"); sr_cnt <= 7; tx_state <= HEADER; end if; when HEADER => -- Wait for sync header + prepare MAC header if (phy_out.tx_data_ack = '1') and (sr_cnt = 0) then -- Sync Header TX complete sr <= mac_in.tx_header.mac_destination & mac_in.tx_header.mac_source & mac_in.tx_header.mac_ethertype; crc_valid <= '1'; sr_cnt <= SR_CNT_MAX; tx_state <= DATA; end if; byte_cnt <= BYTE_CNT_MAX; when DATA => -- Wait for MAC header + transmit payload until tx_mac_data_en goes away if (phy_out.tx_data_ack = '1') and (sr_cnt = 0) then -- MAC Header TX complete if more_data then sr(0) <= mac_in.tx_mac_data; mac_out.tx_mac_data_ack <= '1'; else tx_state <= PAD; end if; end if; when PAD => -- Wait for PADs / last payload byte + prepare CRC if (byte_cnt = 0) then sr(0 to 3) <= (crc(7 downto 0), crc(15 downto 8), crc(23 downto 16), crc(31 downto 24)); sr_cnt <= 4 - 1; tx_state <= TXCRC; end if; when TXCRC => -- Wait for CRC + jump back to idle if (phy_out.tx_data_ack = '1') and (sr_cnt = 0) then -- CRC TX complete tx_state <= IDLE; end if; end case; end if; end process tx_main; phy_in.tx_data_en <= '1' when tx_state /= IDLE else '0'; crc_clear <= '1' when tx_state = HEADER else '0'; phy_in.tx_data <= sr(sr'low); mac_out.tx_active <= phy_out.tx_active; end block tx; end architecture rtl;