library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.bench_pkg.all; library trashernet; use trashernet.trashernet_types.all; entity bench_trashernet_mac is end entity bench_trashernet_mac; architecture bench of bench_trashernet_mac is signal clk : std_logic; signal phy_clk : std_logic; signal rst : std_logic; signal rx_data : std_logic_vector(7 downto 0); signal rx_data_valid : std_logic; signal rx_active : std_logic; signal tx_data : std_logic_vector(7 downto 0); signal tx_data_en : std_logic; signal tx_data_ack : std_logic; signal tx_active : std_logic; signal carrier_detect : std_logic; signal rx_error : std_logic; signal rx_p : std_logic; signal tx_p : std_logic; signal tx_n : std_logic; signal rx_mac_destination : mac_addr_t; signal rx_mac_source : mac_addr_t; signal rx_mac_ethertype : ethertype_t; signal rx_mac_data : byte; signal rx_mac_valid : std_logic; signal rx_mac_crc_ok : std_logic; signal rx_mac_crc_error : std_logic; begin trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc generic map( F_CLK => 49000000, F_CLK_PHY => 100000000 ) port map( clk => clk, phy_clk => phy_clk, rst => rst, rx_data => rx_data, rx_data_valid => rx_data_valid, rx_active => rx_active, tx_data => tx_data, tx_data_en => tx_data_en, tx_data_ack => tx_data_ack, carrier_detect => carrier_detect, rx_error => rx_error, rx_p => rx_p, tx_p => tx_p, tx_n => tx_n ); trashernet_mac_inst : entity trashernet.trashernet_mac port map( clk => clk, rst => rst, rx_data => rx_data, rx_data_valid => rx_data_valid, rx_active => rx_active, tx_data => tx_data, tx_data_en => tx_data_en, tx_data_ack => tx_data_ack, tx_active => tx_active, carrier_detect => carrier_detect, rx_error => rx_error, rx_mac_destination => rx_mac_destination, rx_mac_source => rx_mac_source, rx_mac_ethertype => rx_mac_ethertype, rx_mac_data => rx_mac_data, rx_mac_valid => rx_mac_valid, rx_mac_crc_ok => rx_mac_crc_ok, rx_mac_crc_error => rx_mac_crc_error ); clock_driver : process constant period : time := 20 ns; begin clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2; end process clock_driver; phy_clock_driver : process constant period : time := 10 ns; begin phy_clk <= '0'; wait for period / 2; phy_clk <= '1'; wait for period / 2; end process phy_clock_driver; test : process is begin rx_p <= '0'; rst <= '1'; wait for 20 ns; rst <= '0'; wait for 20 ns; send_data(rx_p, byte_vector'( x"55", x"55", x"55", x"D5", x"11", x"22", x"33", x"44", x"55", x"66", x"00", x"e0", x"4c", x"36", x"00", x"2f", x"08", x"00", x"45", x"00", x"00", x"54", x"fe", x"22", x"40", x"00", x"40", x"01", x"f5", x"28", x"c0", x"a8", x"63", x"0a", x"c0", x"a8", x"63", x"02", x"08", x"00", x"90", x"e6", x"00", x"06", x"00", x"01", x"da", x"bd", x"2c", x"61", x"00", x"00", x"00", x"00", x"9f", x"20", x"02", x"00", x"00", x"00", x"00", x"00", x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b", x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28", x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35", x"36", x"37", x"e9", x"f2", x"6b", x"30" )); send_data(rx_p, byte_vector'( x"55", x"55", x"55", x"D5", x"11", x"22", x"33", x"44", x"55", x"66", x"00", x"e0", x"4c", x"36", x"00", x"2f", x"08", x"00", x"45", x"00", x"00", x"54", x"ca", x"78", x"40", x"00", x"40", x"01", x"28", x"d4", x"c0", x"a8", x"63", x"0a", x"c0", x"a8", x"63", x"01", x"08", x"00", x"93", x"f5", x"00", x"03", x"00", x"01", x"3c", x"bc", x"2c", x"61", x"00", x"00", x"00", x"00", x"38", x"16", x"04", x"00", x"00", x"00", x"00", x"00", x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b", x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28", x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35", x"36", x"37", x"b9", x"7f", x"c7", x"91" )); send_data(rx_p, byte_vector'( x"55", x"55", x"55", x"D5", x"12", x"34", x"56", x"78", x"90", x"12", x"AB", x"CD", x"EF", x"AA", x"BB", x"CC", x"08", x"00", x"11", x"22", x"33", x"44", x"55", x"66", x"CC", x"2C", x"CC", x"2C" )); wait; end process test; receiver : process is begin wait until rising_edge(clk); if rx_data_valid then report "[PHY] RX byte: " & to_hstring(rx_data); end if; if rx_mac_valid then report "[MAC] RX byte: " & to_hstring(rx_mac_data); end if; if rx_mac_crc_ok then report "[MAC] RX CRC OK"; end if; if rx_mac_crc_error then report "[MAC] RX CRC error"; end if; end process receiver; end architecture bench;