-- -------------------------------------------------------------------------- -- -- TRASHERNET - A Trashy Ethernet Stack for FPGAs -- -- -------------------------------------------------------------------------- -- -- synchronizer.vhd : Basic shift-register based synchronizer -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity synchronizer is generic( SIZE : integer := 3 ); port( clk : in std_logic; rst : in std_logic; data_in : in std_logic; data_out : out std_logic ); end entity synchronizer; architecture RTL of synchronizer is signal sr : std_logic_vector(SIZE - 1 downto 0); begin sync : process(clk, rst) is begin if rst then sr <= (others => '0'); elsif rising_edge(clk) then sr <= sr(sr'high - 1 downto sr'low) & data_in; end if; end process sync; data_out <= sr(sr'high); end architecture RTL;