-- -------------------------------------------------------------------------- -- -- TRASHERNET - A Trashy Ethernet Stack for FPGAs -- -- -------------------------------------------------------------------------- -- -- trashernet_mac.vhd : Ethernet OSI Layer 2, Data Link -- Implements packet handling and MAC-Layer en/decoding. -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.trashernet_pkg.all; entity trashernet_mac is port( -- Global clk : in std_logic; -- Global clock rst : in std_logic; -- Asynchronous reset -- PHY signals rx_data : in byte; -- RX Data rx_data_valid : in std_logic; -- RX Data valid rx_active : in std_logic; -- RX of packet in progress tx_data : out byte; -- TX Data tx_data_en : out std_logic; -- Transmitter enable tx_data_ack : in std_logic; -- Latched data_tx tx_active : in std_logic; -- Transmitter active carrier_detect : in std_logic; -- Carrier detected rx_error : in std_logic; -- Receive error -- MAC signals rx_header : out mac_header_fields; -- RX MAC Header Data rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid rx_mac_data : out byte; -- Ethernet data (after Ethertype) rx_mac_valid : out std_logic; -- `rx_mac` values (headers + data) are valid rx_mac_crc_ok : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields) rx_mac_crc_error : out std_logic; -- End of packet, CRC invalid tx_header : in mac_header_fields; -- TX MAC Header Data tx_mac_data : in byte; -- Payload tx_mac_data_en : in std_logic; -- Start (and keep) transmitting a frame tx_mac_data_ack : out std_logic -- The byte on `tx_mac_data` has been latched. Update to next word. ); end entity trashernet_mac; architecture rtl of trashernet_mac is constant ETH_POLYNOMIAL : std_logic_vector(31 downto 0) := x"04C11DB7"; begin rx : block type state_t is (HEAD, PAYLOAD); constant HEAD_LENGTH : integer := rx_header.mac_destination'length + rx_header.mac_source'length + rx_header.mac_ethertype'length; constant CRC_LENGTH : integer := 4; signal state : state_t; signal sr_head : byte_vector(0 to HEAD_LENGTH - 1); constant BYTE_COUNT_MAX : integer := maximum(HEAD_LENGTH, CRC_LENGTH) - 1; signal byte_count : integer range 0 to BYTE_COUNT_MAX; signal sr_payload : byte_vector(0 to 4); signal crc : std_logic_vector(ETH_POLYNOMIAL'range); signal crc_ok : std_logic; signal crc_clear : std_logic; begin crc_inst : entity work.crc generic map( POLYNOMIAL => ETH_POLYNOMIAL, START => x"FFFFFFFF", FINAL_XOR => x"FFFFFFFF", REVERSE_OUT => true ) port map( clk => clk, rst => rst, data => rx_data, data_valid => rx_data_valid, crc_clear => crc_clear, crc_out => crc ); crc_ok <= '1' when crc = x"2144DF1C" else '0'; main : process(clk, rst) is begin if rst then byte_count <= 0; rx_mac_valid <= '0'; rx_mac_crc_error <= '0'; rx_mac_crc_ok <= '0'; rx_mac_header_rcv <= '0'; crc_clear <= '0'; elsif rising_edge(clk) then rx_mac_valid <= '0'; rx_mac_crc_error <= '0'; rx_mac_crc_ok <= '0'; rx_mac_header_rcv <= '0'; crc_clear <= '0'; case state is when HEAD => if rx_data_valid then sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & rx_data; if byte_count = (HEAD_LENGTH - 1) then state <= PAYLOAD; byte_count <= 0; rx_mac_header_rcv <= '1'; end if; if (byte_count /= BYTE_COUNT_MAX) then byte_count <= byte_count + 1; end if; end if; when PAYLOAD => if rx_data_valid then sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & rx_data; if byte_count = CRC_LENGTH then rx_mac_valid <= '1'; else byte_count <= byte_count + 1; end if; end if; if not rx_active then rx_mac_crc_ok <= crc_ok; rx_mac_crc_error <= not crc_ok; end if; if rx_error then rx_mac_crc_error <= '1'; end if; end case; if (not rx_active) or rx_error then byte_count <= 0; state <= HEAD; crc_clear <= '1'; end if; end if; end process main; rx_header.mac_destination <= sr_head(0 to 5); rx_header.mac_source <= sr_head(6 to 11); rx_header.mac_ethertype <= sr_head(12 to 13); rx_mac_data <= sr_payload(0); end block rx; tx : block type tx_state_t is (IDLE, HEADER, DATA, TXCRC); signal tx_state : tx_state_t; signal sr : byte_vector(0 to tx_header.mac_destination'length + tx_header.mac_source'length + tx_header.mac_ethertype'length - 1); constant BIT_CNT_MAX : integer := sr'high; signal byte_cnt : integer range 0 to BIT_CNT_MAX; signal crc : std_logic_vector(ETH_POLYNOMIAL'range); signal crc_clear : std_logic; signal crc_valid : std_logic; begin crc_inst : entity work.crc generic map( POLYNOMIAL => ETH_POLYNOMIAL, START => x"FFFFFFFF", FINAL_XOR => x"FFFFFFFF", REVERSE_OUT => true ) port map( clk => clk, rst => rst, data => tx_data, data_valid => crc_valid, crc_clear => crc_clear, crc_out => crc ); tx_main : process(clk, rst) is begin if rst then tx_mac_data_ack <= '0'; elsif rising_edge(clk) then tx_mac_data_ack <= '0'; crc_valid <= '0'; if tx_data_ack then sr <= sr(sr'low + 1 to sr'high) & x"00"; crc_valid <= '1'; if byte_cnt /= 0 then byte_cnt <= byte_cnt - 1; end if; end if; case tx_state is when IDLE => if not tx_active and tx_mac_data_en then sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5"); byte_cnt <= 7; tx_state <= HEADER; end if; when HEADER => if (tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete sr <= tx_header.mac_destination & tx_header.mac_source & tx_header.mac_ethertype; crc_valid <= '1'; byte_cnt <= BIT_CNT_MAX; tx_state <= DATA; end if; when DATA => if (tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete if tx_mac_data_en then sr(0) <= tx_mac_data; tx_mac_data_ack <= '1'; else sr(0 to 3) <= (crc(7 downto 0), crc(15 downto 8), crc(23 downto 16), crc(31 downto 24)); byte_cnt <= 4 - 1; tx_state <= TXCRC; end if; end if; when TXCRC => if (tx_data_ack = '1') and (byte_cnt = 0) then -- CRC TX complete tx_state <= IDLE; end if; end case; end if; end process tx_main; tx_data_en <= '1' when tx_state /= IDLE else '0'; crc_clear <= '1' when tx_state = HEADER else '0'; tx_data <= sr(sr'low); end block tx; end architecture rtl;