105 lines
2.7 KiB
VHDL
105 lines
2.7 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- bench_trashernet_phy.vhd : Cocotb test bench for the PHY
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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entity cocotb_trashernet_phy is
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end entity cocotb_trashernet_phy;
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architecture bench of cocotb_trashernet_phy is
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signal clk : std_logic;
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signal phy_clk : std_logic;
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signal rst : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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-- Cocotb interface
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signal coco_dut_rxd : std_logic_vector(7 downto 0); -- RX data
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signal coco_dut_rxs : std_logic := '0'; -- RX toggle
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signal coco_dut_rxa : std_logic; -- RX active
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signal coco_tb_txd : std_logic_vector(7 downto 0); -- TX data
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signal coco_tb_txs : std_logic := '0'; -- TX toggle
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signal coco_tb_txa : std_logic := '0'; -- TX done toggle
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begin
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-- Instantiate design
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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F_CLK => 49000000,
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F_CLK_PHY => 100000000
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)
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port map(
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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-- Create infrastructure
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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phy_clock_driver : process
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constant period : time := 10 ns;
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begin
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phy_clk <= '0';
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wait for period / 2;
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phy_clk <= '1';
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wait for period / 2;
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end process phy_clock_driver;
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-- Cocotb adapter (ETH)
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test : process is
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begin
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rx_p <= '0';
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loop
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wait on coco_tb_txs;
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for j in coco_tb_txd'low to coco_tb_txd'high loop
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rx_p <= not coco_tb_txd(j);
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wait for 50 ns;
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rx_p <= coco_tb_txd(j);
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wait for 50 ns;
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end loop;
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coco_tb_txa <= not coco_tb_txa;
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end loop;
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end process test;
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receiver : process is
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begin
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wait until rising_edge(clk);
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if phy_out.rx_data_valid then
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coco_dut_rxd <= phy_out.rx_data;
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coco_dut_rxs <= not coco_dut_rxs;
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end if;
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end process receiver;
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coco_dut_rxa <= phy_out.rx_active;
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end architecture bench;
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