fpga/trashernet
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Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers, including physical!
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README.MD

Trashernet

Trashernet Logo

Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers:

  • Layer 1, Physical: trashernet_phy
  • Layer 2, Data link: trashernet_mac

When writing it, the following were the main design philosophies:

  1. Standards are nice and all, but this, it just needs to work.
  2. Hardware is expensive, LOC are not. So let's do everything we can inside the FPGA.
  3. If there's a feature that feels optional even though it isn't, it is. See 1. if in doubt.

IMPORTANT: This code (and HW suggestions) violate the Ethernet standard in many ways. Do not use in proper (especially commercial) products.

Hardware

Circuit Diagram

  • RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL. Also, pull up/down resistors help to avoid glitchy behavior with no cable connected or little data activity.
  • TX: Meh, a series current limiting resistor is good enough. Drive two outputs differentially to increase the voltage swing. (Technically not true antivalent signals as there's also the "off" state with both disabled.)

Notes:

  • The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
  • On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D

License

This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.