diff --git a/SERV-SoC.md b/Tiny-RISCV-SoC-for-RFU.md
similarity index 82%
rename from SERV-SoC.md
rename to Tiny-RISCV-SoC-for-RFU.md
index 4fb9ce5..42042a4 100644
--- a/SERV-SoC.md
+++ b/Tiny-RISCV-SoC-for-RFU.md
@@ -1,4 +1,4 @@
-# Basic Concept
+# SERV
 
 Build a "servant". Maybe from fusesoc if I can figure out how, or just manually from source. Should be easy. Has everything I need to get started, so I might not even have to worry about getting my VHDL into the Verilog top level.
 
@@ -6,16 +6,20 @@ Then run zephyr OS on it. ttps://github.com/olofk/serv has the instructions on t
 
 ZephyrOS seems to also include some RSA implementations, so that's useful.
 
-# Commands
+## Commands
 
 * Build SERVANT for CMOD A7: `fusesoc run --tool=vivado --target=cmod_a7_35t servant`
 * For faster RISCV-IM add multiply divide from `fusesoc library add mdu https://github.com/zeeshanrafique23/mdu`
 
-# Links
+## Links
 
 * https://github.com/olofk/serv
 * https://fusesoc.readthedocs.io/en/stable/user/overview.html
 
-# Interesting Reads
+## Interesting Reads
 
-* https://riscv.org/blog/2022/07/risc-v-compressed-instructions-for-serv-abdul-wadood-lfx-mentorship-at-risc-v-international/
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+* https://riscv.org/blog/2022/07/risc-v-compressed-instructions-for-serv-abdul-wadood-lfx-mentorship-at-risc-v-international/
+
+# PicoRV32
+
+Might be an interesting alternative.
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