Combination BA is not possible, will be BB instead.
Swap A and B on second MUX per chip to fix.
Actually, that's not quite correct. To get the LUT Output Muxing table as shown besides the MUX, pin 12 (currently B) needs to be removed from the pad and shorted to pin 13 (A) next to it. Luckily, that bodge super easy to perform.
More thoughts on this. If I do this, I can never drive B to net 1 or 3. Essentially not a big deal as we can just swap LUT3-1 and LUT3-2 in SW.
But then, look at the second MUX. If we swap and drive the now-A to net 1, we cannot drive B to net 3. So maybe leave MUX U10 net 3 as is, and change the net-2 routing.
That way, I could ONLY drive B to net 2, but thanks to the LUT-swappery described above this may be OK.
Check the following: Cut U7 pin 12 (B), connect to 13 (A). Cut U10 pin 5 (A), connect to pin 4 (B).
Another idea: Cut U7 pin 12 (B), connect to 13 (A). Cut U10 pin 13 (A), connect to 12 (B).
This gives us full flexibility on the first unit (using LUT swapping), and it guarantees full usability of the second LUT even when driving net-1 from LUT-0 (LUT-1 can be connected to either of the nets).
Only problem: net-2 and net-3 can never have the A/B combination.
PS: Forget it, this is BS. The first change is good. The second one doesn't help with the problem at hand -- that being the B-B connection. And there actually ain't a good way to bodgefix this. So I suppose we just leave the second chip as is. (Only A can be routed to net-1, so we should be able to route B to either 3 or 4.) The only downside to this will be that the combination of A/B is impossible or net-2/net-3. Unless everything is async.....
The only real solution is to Cut U7 pin 12 (B), connect to 13 (A) for the upper LUT, and then modify LUT-2 to use a_async. This should give us true full flexibility.
Updated schematic to include bodge-fix in commit 4424d762f7.
Kousaten has the fix since commit f27c728472.