main.c 3.3 KB

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  1. #include <stdio.h>
  2. #include "fpga_cell.h"
  3. #include "fpga_fdef_loader.h"
  4. #include "fpga_global.h"
  5. #include "fpga.h"
  6. #include "unistd.h"
  7. #include "string.h"
  8. #include "fpga_cell_lut34.h" /* For testing purposes only */
  9. #define E_FDEF 1
  10. #define E_BITSTREAM 2
  11. static void test_design_cell_ripple(struct fpga_cell_lut34 *cell, int first, int last)
  12. {
  13. cell->lut_in_sel[0] = LUT_NET_F0; // Own state
  14. cell->lut_in_sel[1] = LUT_NET_F2; // Feedback &-net -- just for fun
  15. cell->lut_in_sel[2] = (first ? LUT_NET_T2 : LUT_NET_L1); // &-state of previous stages
  16. cell->lut_in_sel[3] = LUT_NET_L0; // Previous state -- just for fun
  17. cell->sync = 1;
  18. cell->drive_sel[0] = 'A';
  19. cell->drive_sel[1] = 'b';
  20. cell->drive_sel[2] = (last ? 'b' : 'Z');
  21. cell->drive_sel[3] = 'Z';
  22. cell->route_en = (1 << ROUTE_L2);
  23. cell->LUT3[0] = 0b01011010;
  24. cell->LUT3[1] = 0b10100000;
  25. }
  26. // WARNING: Requires a >=4x4 FPGA FDEF!
  27. static void test_design_counter(struct fpga_cell *entry_cell)
  28. {
  29. struct fpga_cell_lut34 *cell;
  30. int i, j;
  31. for (i = 0; i < 4; ++i) {
  32. cell = ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]));
  33. for (j = 4 - i; j < 4; ++j) {
  34. cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[BOTTOM];
  35. }
  36. test_design_cell_ripple(cell, 1, 0);
  37. cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
  38. test_design_cell_ripple(cell, 0, 0);
  39. cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
  40. test_design_cell_ripple(cell, 0, 0);
  41. cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
  42. test_design_cell_ripple(cell, 0, 1);
  43. }
  44. }
  45. int development_test_main(int argc, char *argv[])
  46. {
  47. struct fpga_cell *entry_cell;
  48. struct fpga_chain *chain;
  49. int opt;
  50. char *fdef_filename = "fdef/4x4.fdef";
  51. char *kst_filename = "-";
  52. char *bitstream_filename = "-";
  53. int bitstream_ascii = 0;
  54. set_log_level(LL_DEBUG);
  55. while((opt = getopt(argc, argv, "f:i:o:h")) != -1)
  56. {
  57. switch(opt)
  58. {
  59. case 'f':
  60. fdef_filename = optarg;
  61. break;
  62. case 'i':
  63. kst_filename = optarg;
  64. report(LL_WARNING, "Input not yet implemented.");
  65. break;
  66. case 'o':
  67. bitstream_filename = optarg;
  68. break;
  69. case 'h':
  70. bitstream_ascii = 1;
  71. break;
  72. case ':':
  73. case '?':
  74. printf("Usage: %s [-f fdef] [-i input.kst] [-o output.bin] [-h]\n"
  75. "Generate bitstreams for the TTL-FPGA.\n\n"
  76. "When INPUT or OUTPUT is -, read/write standard input.\n\n"
  77. " -f\tFDEF FPGA description file, default fdef/4x4.fdef\n"
  78. " -i\tKousaten input file, default stdin\n"
  79. " -o\tOutput file, default stdout\n"
  80. " -h\tGenerate output as ASCII HEX\n",
  81. argv[0]);
  82. return 0;
  83. default:
  84. break;
  85. }
  86. }
  87. entry_cell = fpga_fdef_loader_load(fdef_filename);
  88. if (!entry_cell) {
  89. report(LL_CRITICAL, "Error loading FDEF.");
  90. return E_FDEF;
  91. }
  92. report(LL_INFO, "FDEF loaded.");
  93. chain = fpga_isp_chain_new(entry_cell);
  94. if (!chain) {
  95. report(LL_CRITICAL, "Critical error during bitstream generation.");
  96. return E_BITSTREAM;
  97. }
  98. report(LL_INFO, "Chain loaded.");
  99. test_design_counter(entry_cell);
  100. if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) {
  101. report(LL_ERROR, "Bitstream generation failed.");
  102. return E_BITSTREAM;
  103. }
  104. report(LL_INFO, "Generated bitstream.");
  105. return 0;
  106. }
  107. int main(int argc, char *argv[])
  108. {
  109. return development_test_main(argc, argv);
  110. }