This commit is contained in:
Markus Koch 2016-02-19 21:35:21 +01:00
parent f87e53ce93
commit 17abef7788
12 changed files with 2555 additions and 1617 deletions

1
.gitignore vendored
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@ -3,3 +3,4 @@ shimatta-libs
*.bck *.bck
*.kicad_pcb-bak *.kicad_pcb-bak
_saved* _saved*
_autosave*

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@ -42,7 +42,7 @@ EELAYER 25 0
EELAYER END EELAYER END
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Sheet 4 7 Sheet 4 8
Title "" Title ""
Date "" Date ""
Rev "" Rev ""
@ -528,4 +528,32 @@ Text HLabel 2950 4950 2 60 Output ~ 0
A[19..23] A[19..23]
Text HLabel 2600 2650 2 60 Output ~ 0 Text HLabel 2600 2650 2 60 Output ~ 0
SDIO_CMD SDIO_CMD
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Text HLabel 2300 1850 2 60 Output ~ 0
T_CS
Text HLabel 2300 1950 2 60 Output ~ 0
T_CLK
Text HLabel 2300 2050 2 60 Input ~ 0
T_DOUT
Text HLabel 2300 2150 2 60 Output ~ 0
T_DIN
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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@ -42,7 +42,7 @@ EELAYER 25 0
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@ -42,7 +42,7 @@ EELAYER 25 0
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@ -232,33 +232,17 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
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Wire Wire Line Wire Wire Line
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Text Label 4650 2100 0 60 ~ 0
SD_SCK
Wire Wire Line Wire Wire Line
5000 2200 4650 2200 5000 2800 4600 2800
Wire Wire Line Wire Wire Line
5000 2300 4650 2300 5000 2900 4600 2900
Wire Wire Line Wire Wire Line
5000 2400 4650 2400 5000 3000 4600 3000
Text Label 4650 2200 0 60 ~ 0
SD_SO
Text Label 4650 2300 0 60 ~ 0
SD_SI
Text Label 4650 2400 0 60 ~ 0
SD_NSS
Wire Wire Line Wire Wire Line
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Wire Wire Line Wire Wire Line
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Wire Wire Line
5000 2900 4650 2900
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Wire Wire Line
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Wire Wire Line
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Text Label 4650 2700 0 60 ~ 0 Text Label 4650 2700 0 60 ~ 0
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Text Label 4650 2800 0 60 ~ 0 Text Label 4650 2800 0 60 ~ 0
@ -474,4 +458,20 @@ F 3 "" H 1250 7450 50 0000 C CNN
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$EndComp $EndComp
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NoConn ~ 5000 2100
NoConn ~ 5000 2200
NoConn ~ 5000 2300
NoConn ~ 5000 2400
Text HLabel 4600 2700 0 60 Input ~ 0
T_CLK
Text HLabel 4600 2800 0 60 Input ~ 0
T_CS
Text HLabel 4600 2900 0 60 Input ~ 0
T_DIN
Text HLabel 4600 3000 0 60 Output ~ 0
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Text HLabel 4600 3100 0 60 Output ~ 0
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@ -377,6 +377,49 @@ X VI 3 -400 50 150 R 40 40 1 1 W
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# LED_RGB
#
DEF LED_RGB D 0 0 Y Y 1 F N
F0 "D" 0 425 50 H V C CNN
F1 "LED_RGB" 0 350 50 H V C CNN
F2 "" 0 -50 50 H V C CNN
F3 "" 0 -50 50 H V C CNN
DRAW
T 0 -75 -250 50 0 0 0 B Normal 0 C C
T 0 -75 -50 50 0 0 0 G Normal 0 C C
T 0 -75 150 50 0 0 0 R Normal 0 C C
S 50 -50 50 50 0 1 0 N
S 50 50 50 50 0 1 0 N
S 50 150 50 250 0 1 0 N
S 50 250 50 250 0 1 0 N
S 100 300 -100 -300 0 1 0 f
P 2 0 1 0 -50 -200 -100 -200 N
P 2 0 1 0 -50 -150 -50 -250 N
P 2 0 1 0 -50 0 -100 0 N
P 2 0 1 0 -50 200 -100 200 N
P 2 0 1 0 50 -200 100 -200 N
P 2 0 1 0 50 0 100 0 N
P 2 0 1 0 50 200 100 200 N
P 3 0 1 0 -50 50 -50 -50 -50 -50 N
P 3 0 1 0 -50 250 -50 150 -50 150 N
P 4 0 1 0 -53 -116 -73 -116 -53 -126 -53 -126 N
P 4 0 1 0 -40 80 -60 80 -40 70 -40 70 N
P 4 0 1 0 -40 280 -60 280 -40 270 -40 270 N
P 5 0 1 0 20 -150 -30 -140 -20 -130 -60 -120 -60 -120 N
P 5 0 1 0 50 -150 50 -250 -50 -200 50 -150 50 -150 F
P 6 0 1 0 20 50 -30 60 -20 70 -60 80 -60 80 -60 80 N
P 6 0 1 0 20 250 -30 260 -20 270 -60 280 -60 280 -60 280 N
P 6 0 1 0 50 50 50 -50 -50 0 50 50 50 50 50 50 F
P 6 0 1 0 50 250 50 150 -50 200 50 250 50 250 50 250 F
X RC 1 -200 200 100 R 50 50 1 1 P
X GC 2 -200 0 100 R 50 50 1 1 P
X BC 3 -200 -200 100 R 50 50 1 1 P
X BA 4 200 -200 100 L 50 50 1 1 P
X GA 5 200 0 100 L 50 50 1 1 P
X RA 6 200 200 100 L 50 50 1 1 P
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#
# LFXP2-5E-6TN144C # LFXP2-5E-6TN144C
# #
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@ -852,6 +895,21 @@ X BOOT0 94 -200 -450 200 R 50 50 7 1 I
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# SW_PUSH
#
DEF SW_PUSH SW 0 40 N N 1 F N
F0 "SW" 150 110 50 H V C CNN
F1 "SW_PUSH" 0 -80 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
S -170 50 170 60 0 1 0 N
P 4 0 1 0 -40 60 -30 90 30 90 40 60 N
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X 2 2 300 0 200 L 50 50 0 1 P I
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#
# TCXO_DFAS11 # TCXO_DFAS11
# #
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1333
fpgna.net

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@ -42,7 +42,7 @@ EELAYER 25 0
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$Descr A4 11693 8268 $Descr A4 11693 8268
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Title "FPGna" Title "FPGna"
Date "" Date ""
Rev "" Rev ""
@ -65,54 +65,104 @@ F6 "CLK_50M" O L 1100 1950 60
F7 "FPGA_ENABLE_N" I R 3150 2450 60 F7 "FPGA_ENABLE_N" I R 3150 2450 60
$EndSheet $EndSheet
$Sheet $Sheet
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U 56337D98 U 56337D98
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F1 "debug.sch" 60 F1 "debug.sch" 60
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F3 "JTMS" O R 6700 1400 60 F3 "JTMS" O R 6150 4050 60
F4 "JTDO" I R 6700 1500 60 F4 "JTDO" I R 6150 4150 60
F5 "JTCK" O R 6700 1600 60 F5 "JTCK" O R 6150 4250 60
F6 "JRST_N" I R 6700 1700 60 F6 "JRST_N" I R 6150 4350 60
F7 "BOOT1" O R 6700 1900 60 F7 "BOOT1" O R 6150 4550 60
$EndSheet $EndSheet
$Sheet $Sheet
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U 56C43C85 U 56C43C85
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F5 "BL0_N" O R 9300 2350 60 F5 "BL0_N" O R 8350 2350 60
F6 "BL1_N" O R 9300 2450 60 F6 "BL1_N" O R 8350 2450 60
F7 "A[19..23]" O R 9300 2550 60 F7 "A[19..23]" O R 8350 2550 60
F8 "SDIO_CMD" O L 6300 1800 60
F9 "T_CS" O R 8350 1350 60
F10 "T_CLK" O R 8350 1250 60
F11 "T_DOUT" I R 8350 1550 60
F12 "T_DIN" O R 8350 1450 60
$EndSheet $EndSheet
$Sheet $Sheet
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U 56C579FC U 56C579FC
F0 "display" 60 F0 "display" 60
F1 "display.sch" 60 F1 "display.sch" 60
F2 "T_CLK" I L 8500 1250 60
F3 "T_CS" I L 8500 1350 60
F4 "T_DIN" I L 8500 1450 60
F5 "T_DOUT" O L 8500 1550 60
F6 "T_BUSY" O R 10250 1350 60
F7 "T_IRQ" O R 10250 1250 60
$EndSheet $EndSheet
$Sheet $Sheet
S 9550 2200 1300 450 S 8600 2200 1300 450
U 56C6F777 U 56C6F777
F0 "sdram" 60 F0 "sdram" 60
F1 "sdram.sch" 60 F1 "sdram.sch" 60
F2 "A[19..23]" I L 9550 2550 60 F2 "A[19..23]" I L 8600 2550 60
F3 "BL0_N" I L 9550 2350 60 F3 "BL0_N" I L 8600 2350 60
F4 "BL1_N" I L 9550 2450 60 F4 "BL1_N" I L 8600 2450 60
$EndSheet $EndSheet
Wire Bus Line Wire Bus Line
9550 2550 9300 2550 8600 2550 8350 2550
Wire Wire Line Wire Wire Line
9300 2350 9550 2350 8350 2350 8600 2350
Wire Wire Line Wire Wire Line
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$Sheet $Sheet
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U 56C86141
F0 "userif" 60
F1 "userif.sch" 60
$EndSheet
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S 4600 1650 1400 800
U 56C7DD81 U 56C7DD81
F0 "sdcard" 60 F0 "sdcard" 60
F1 "sdcard.sch" 60 F1 "sdcard.sch" 60
F2 "SDIO_CMD" I R 6000 1800 60
F3 "T_IRQ" I L 4600 1800 60
F4 "T_BUSY" I L 4600 1900 60
$EndSheet $EndSheet
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4500 1800 4600 1800
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Wire Wire Line
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@ -42,7 +42,7 @@ EELAYER 25 0
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@ -42,7 +42,7 @@ EELAYER 25 0
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Title "" Title ""
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@ -55,17 +55,17 @@ $EndDescr
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L STM32F407VGT U? L STM32F407VGT U?
U 4 1 56C7DE2F U 4 1 56C7DE2F
P 5150 2450 P 5800 2450
AR Path="/56C43C85/56C7DE2F" Ref="U?" Part="4" AR Path="/56C43C85/56C7DE2F" Ref="U?" Part="4"
AR Path="/56C7DD81/56C7DE2F" Ref="U4" Part="4" AR Path="/56C7DD81/56C7DE2F" Ref="U4" Part="4"
F 0 "U4" H 5928 1653 60 0000 L CNN F 0 "U4" H 6578 1653 60 0000 L CNN
F 1 "STM32F407VGT" H 5928 1547 60 0000 L CNN F 1 "STM32F407VGT" H 6578 1547 60 0000 L CNN
F 2 "footprints:LQFP-100_14x14mm_Pitch0.5mm-SMALLCORNER" H 4650 2950 60 0001 C CNN F 2 "footprints:LQFP-100_14x14mm_Pitch0.5mm-SMALLCORNER" H 5300 2950 60 0001 C CNN
F 3 "" H 4650 2950 60 0000 C CNN F 3 "" H 5300 2950 60 0000 C CNN
4 5150 2450 4 5800 2450
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@ -110,10 +110,10 @@ Wire Wire Line
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$Comp $Comp
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F 2 "" H 3450 3900 50 0000 C CNN F 2 "" H 3450 3900 50 0000 C CNN
F 3 "" H 3450 3900 50 0000 C CNN F 3 "" H 3450 3900 50 0000 C CNN
@ -121,10 +121,10 @@ F 3 "" H 3450 3900 50 0000 C CNN
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F 1 "VSTM33" H 3568 2774 50 0000 C CNN F 1 "VSTM33" H 3568 2774 50 0000 C CNN
F 2 "" H 3550 2600 50 0000 C CNN F 2 "" H 3550 2600 50 0000 C CNN
F 3 "" H 3550 2600 50 0000 C CNN F 3 "" H 3550 2600 50 0000 C CNN
@ -165,10 +165,10 @@ Wire Wire Line
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$Comp $Comp
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U 1 1 56C7E8BC U 1 1 56C7E8BC
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F 2 "" H 3850 3900 50 0000 C CNN F 2 "" H 3850 3900 50 0000 C CNN
F 3 "" H 3850 3900 50 0000 C CNN F 3 "" H 3850 3900 50 0000 C CNN
@ -187,10 +187,10 @@ Wire Wire Line
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$Comp $Comp
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@ -198,27 +198,35 @@ F 3 "" H 3850 2600 50 0000 C CNN
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Wire Wire Line Wire Wire Line
4950 3450 4450 3450 5600 3450 5100 3450
Text Label 4450 3450 0 60 ~ 0 Text Label 5100 3450 0 60 ~ 0
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Wire Wire Line Wire Wire Line
4950 3550 4450 3550 5600 3550 5100 3550
Text Label 4450 3550 0 60 ~ 0 Text Label 5100 3550 0 60 ~ 0
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Wire Wire Line Wire Wire Line
4950 3650 4450 3650 5600 3650 5100 3650
Text Label 4450 3650 0 60 ~ 0 Text Label 5100 3650 0 60 ~ 0
SDIO_D3 SDIO_D3
Wire Wire Line Wire Wire Line
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4950 2350 4450 2350 5600 2350 5100 2350
Text Label 4450 2350 0 60 ~ 0 Text Label 5100 2350 0 60 ~ 0
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5600 3250 5050 3250
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@ -42,7 +42,7 @@ EELAYER 25 0
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318
userif.sch Normal file
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@ -0,0 +1,318 @@
EESchema Schematic File Version 2
LIBS:fpgna-rescue
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:Oscillators
LIBS:lattice
LIBS:pmic
LIBS:specific-powersyms
LIBS:regulators
LIBS:stm32f4
LIBS:itead-displays
LIBS:ram
LIBS:fpgna-cache
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$EndComp
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$EndComp
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$Comp
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1 3800 3200
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$EndComp
$Comp
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1 0 0 -1
$EndComp
$Comp
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Wire Wire Line
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Wire Wire Line
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$EndComp
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P 7250 3200
F 0 "#PWR805" H 7250 2950 50 0001 C CNN
F 1 "GND" H 7258 3026 50 0000 C CNN
F 2 "" H 7250 3200 50 0000 C CNN
F 3 "" H 7250 3200 50 0000 C CNN
1 7250 3200
1 0 0 -1
$EndComp
$Comp
L GND #PWR806
U 1 1 56C8844A
P 7500 3200
F 0 "#PWR806" H 7500 2950 50 0001 C CNN
F 1 "GND" H 7508 3026 50 0000 C CNN
F 2 "" H 7500 3200 50 0000 C CNN
F 3 "" H 7500 3200 50 0000 C CNN
1 7500 3200
1 0 0 -1
$EndComp
$Comp
L GND #PWR807
U 1 1 56C88450
P 7750 3200
F 0 "#PWR807" H 7750 2950 50 0001 C CNN
F 1 "GND" H 7758 3026 50 0000 C CNN
F 2 "" H 7750 3200 50 0000 C CNN
F 3 "" H 7750 3200 50 0000 C CNN
1 7750 3200
1 0 0 -1
$EndComp
$Comp
L GND #PWR808
U 1 1 56C88456
P 8000 3200
F 0 "#PWR808" H 8000 2950 50 0001 C CNN
F 1 "GND" H 8008 3026 50 0000 C CNN
F 2 "" H 8000 3200 50 0000 C CNN
F 3 "" H 8000 3200 50 0000 C CNN
1 8000 3200
1 0 0 -1
$EndComp
Wire Wire Line
7750 2600 7750 3200
Wire Wire Line
7150 2200 8000 2200
Wire Wire Line
8000 2200 8000 3200
Wire Wire Line
6550 2600 7050 2600
Wire Wire Line
7050 2600 7050 2850
Wire Wire Line
7050 2850 7500 2850
Wire Wire Line
7500 2850 7500 3200
Wire Wire Line
5500 2200 6550 2200
Wire Wire Line
5500 2600 5950 2600
Wire Wire Line
7150 2400 7150 2600
Wire Wire Line
5500 2400 7150 2400
Wire Wire Line
6550 2800 6550 3000
Wire Wire Line
5500 2800 6550 2800
Text Label 5500 2200 0 60 ~ 0
SW_A
Text Label 5500 2400 0 60 ~ 0
SW_D
Text Label 5500 2600 0 60 ~ 0
SW_B
Text Label 5500 2800 0 60 ~ 0
SW_C
Wire Wire Line
7250 3200 7250 3000
Wire Wire Line
7250 3000 7150 3000
$Comp
L LED_RGB D801
U 1 1 56C88B18
P 4100 1200
F 0 "D801" H 4100 1666 50 0000 C CNN
F 1 "LED_RGB" H 4100 1574 50 0000 C CNN
F 2 "" H 4100 1150 50 0001 C CNN
F 3 "" H 4100 1150 50 0000 C CNN
1 4100 1200
1 0 0 -1
$EndComp
$EndSCHEMATC