Wired FSMC on STM side

2016-02-17 10:41:34 +01:00 · 2016-02-17 10:41:34 +01:00 · 4d8213d31b
commit 4d8213d31b
parent 8675a96e87
6 changed files with 906 additions and 528 deletions
--- a/FSMC.sch
+++ b/FSMC.sch
@ -0,0 +1,240 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:Oscillators
+LIBS:lattice
+LIBS:pmic
+LIBS:specific-powersyms
+LIBS:regulators
+LIBS:stm32f4
+LIBS:fpgna-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 4 4
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+Date ""
+Rev ""
+Comp ""
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+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
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+$Comp
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+CLK
+$Comp
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+F 2 "Housings_QFP:TQFP-48_7x7mm_Pitch0.5mm" H 1950 1750 60  0001 C CNN
+F 3 "" H 1950 1750 60  0000 C CNN
+	3    2450 1250
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	2650 2050 3000 2050
+Text Label 3000 2050 2    60   ~ 0
+ADV_N
+Text HLabel 2750 1550 2    60   Input ~ 0
+BOOT1
+Text HLabel 2750 1650 2    60   Input ~ 0
+JTDO
+Text HLabel 2750 1750 2    60   Input ~ 0
+JRST_N
+Wire Wire Line
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+L R R?
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+$EndComp
+Wire Wire Line
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--- a/debug.sch
+++ b/debug.sch
@ -33,12 +33,13 @@ LIBS:lattice
 LIBS:pmic
 LIBS:specific-powersyms
 LIBS:regulators
+LIBS:stm32f4
 LIBS:fpgna-cache
 EELAYER 25 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
-Sheet 3 3
+Sheet 3 4
 Title ""
 Date ""
 Rev ""
@ -49,23 +50,23 @@ Comment3 ""
 Comment4 ""
 $EndDescr
 $Comp
-L Lattice-JTAG P?
+L Lattice-JTAG P3
 U 1 1 56338EF4
 P 4450 1600
-F 0 "P?" H 4250 1250 60  0000 C CNN
+F 0 "P3" H 4250 1250 60  0000 C CNN
 F 1 "Lattice-JTAG" H 4450 1950 60  0000 C CNN
-F 2 "" H 4450 1600 60  0000 C CNN
+F 2 "" H 4450 1600 60  0001 C CNN
 F 3 "" H 4450 1600 60  0000 C CNN
 	1    4450 1600
 	1    0    0    1   
 $EndComp
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+F 0 "U3" H 2900 2700 60  0000 C CNN
 F 1 "LFXP2-5E-6TN144C" H 2900 2600 60  0000 C CNN
-F 2 "" H 2200 2150 60  0000 C CNN
+F 2 "Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm" H 2200 2150 60  0001 C CNN
 F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 1850 3050 60  0001 C CNN
 F 4 "1.0" H -750 2950 60  0001 C CNN "Version"
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@ -81,10 +82,10 @@ Wire Wire Line
 Wire Wire Line
 	4000 1500 3550 1500
 $Comp
-L +3V3 #PWR?
+L +3V3 #PWR44
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 $EndComp
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 Wire Wire Line
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--- a/fpgna-cache.lib
+++ b/fpgna-cache.lib
@ -189,7 +189,7 @@ F3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeX
 F4 "1.0" -3650 1150 60 H I C CNN "Version"
 F5 "Makise Kurisu <kurisu@shimatta.de>" -2850 1050 60 H I C CNN "Author"
 $FPLIST
- TQFP144
+ TQFP-144
 $ENDFPLIST
 DRAW
 T 0 250 650 60 0 2 0 BANK0  Italic 0 C C
@ -423,22 +423,29 @@ X VBAT 10 500 100 200 L 50 50 1 1 w
 ENDDRAW
 ENDDEF
 #
-# Q_NPN_BCE
+# Q_NMOS_DGS
 #
-DEF Q_NPN_BCE Q 0 0 Y N 1 F N
+DEF Q_NMOS_DGS Q 0 0 Y N 1 F N
 F0 "Q" 300 50 50 H V R CNN
-F1 "Q_NPN_BCE" 600 -50 50 H V R CNN
+F1 "Q_NMOS_DGS" 650 -50 50 H V R CNN
 F2 "" 200 100 50 H V C CNN
 F3 "" 0 0 50 H V C CNN
 DRAW
 C 50 0 111 0 1 10 N
-P 2 0 1 0  25 25  100 100 N
-P 3 0 1 0  25 -25  100 -100  100 -100 N
-P 3 0 1 20  25 75  25 -75  25 -75 N
-P 5 0 1 0  50 -70  70 -50  90 -90  50 -70  50 -70 F
-X B 1 -200 0 225 R 50 50 1 1 I
-X C 2 100 200 100 D 50 50 1 1 P
-X E 3 100 -200 100 U 50 50 1 1 P
+P 2 0 1 0  30 -70  100 -70 N
+P 2 0 1 10  30 -50  30 -90 N
+P 2 0 1 0  30 0  100 0 N
+P 2 0 1 10  30 20  30 -20 N
+P 2 0 1 0  30 70  100 70 N
+P 2 0 1 10  30 90  30 50 N
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+P 4 0 1 0  40 0  80 15  80 -15  40 0 F
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 210 R 50 50 1 1 I
+X S 3 100 -200 100 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
@ -486,6 +493,129 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# STM32F407VGT
+#
+DEF STM32F407VGT U 0 40 Y Y 7 L N
+F0 "U" 100 150 60 H V C CNN
+F1 "STM32F407VGT" 350 50 60 H V C CNN
+F2 "" -500 500 60 H V C CNN
+F3 "" -500 500 60 H V C CNN
+DRAW
+T 900 450 -800 60 0 2 0 Port~A  Normal 0 C C
+T 900 450 -800 60 0 3 0 Port~B  Normal 0 C C
+S 0 0 750 -1700 3 0 0 f
+T 900 450 -800 60 0 4 0 Port~C  Normal 0 C C
+S 0 0 750 -1700 4 0 0 f
+T 900 450 -800 60 0 5 0 Port~D  Normal 0 C C
+S 0 0 750 -1700 5 0 0 f
+T 900 450 -800 60 0 6 0 Port~E  Normal 0 C C
+S 0 0 750 -1700 6 0 0 f
+S 0 0 550 -550 7 0 0 f
+S 0 0 500 -1350 1 1 0 f
+X VBAT 6 -200 -1250 200 R 50 50 1 1 W
+X VSS 10 700 -100 200 L 50 50 1 1 W
+X VSSA 20 700 -750 200 L 50 50 1 1 W
+X VDD 50 -200 -400 200 R 50 50 1 1 W
+X VDD 11 -200 -100 200 R 50 50 1 1 W
+X VREF+ 21 -200 -850 200 R 50 50 1 1 W
+X VDDA 22 -200 -750 200 R 50 50 1 1 W
+X VCAP2 73 -200 -1100 200 R 50 50 1 1 W
+X VSS 74 700 -300 200 L 50 50 1 1 W
+X VDD 75 -200 -500 200 R 50 50 1 1 W
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+X VDD 28 -200 -300 200 R 50 50 1 1 W
+X VDD 19 -200 -200 200 R 50 50 1 1 W
+X VCAP1 49 -200 -1000 200 R 50 50 1 1 W
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+X VDD 100 -200 -600 200 R 50 50 1 1 W
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+X PA12 71 -200 -1300 200 R 50 50 2 1 B
+X PA7 32 -200 -800 200 R 50 50 2 1 B
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+X PA1 24 -200 -200 200 R 50 50 2 1 B
+X PA2 25 -200 -300 200 R 50 50 2 1 B
+X PA3 26 -200 -400 200 R 50 50 2 1 B
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+X PA8 67 -200 -900 200 R 50 50 2 1 B
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+X PA9 68 -200 -1000 200 R 50 50 2 1 B
+X PA4 29 -200 -500 200 R 50 50 2 1 B
+X PA10 69 -200 -1100 200 R 50 50 2 1 B
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+X PB8 95 -200 -900 200 R 50 50 3 1 B
+X PB1 36 -200 -200 200 R 50 50 3 1 I
+X PB9 96 -200 -1000 200 R 50 50 3 1 B
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+X PB11 48 -200 -1200 200 R 50 50 3 1 B
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+X PC5 34 -200 -600 200 R 50 50 4 1 B
+X PC7 64 -200 -800 200 R 50 50 4 1 B
+X PC0 15 -200 -100 200 R 50 50 4 1 B
+X PC8 65 -200 -900 200 R 50 50 4 1 B
+X PC1 16 -200 -200 200 R 50 50 4 1 B
+X PC9 66 -200 -1000 200 R 50 50 4 1 B
+X PC2 17 -200 -300 200 R 50 50 4 1 B
+X PC3 18 -200 -400 200 R 50 50 4 1 B
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+X PE0 97 -200 -100 200 R 50 50 6 1 I
+X PE7 38 -200 -800 200 R 50 50 6 1 B
+X PE1 98 -200 -200 200 R 50 50 6 1 I
+X PE8 39 -200 -900 200 R 50 50 6 1 B
+X PH0_OSCIN 12 -200 -100 200 R 50 50 7 1 B
+X PH1_OSCOUT 13 -200 -200 200 R 50 50 7 1 B
+X NRST 14 -200 -350 200 R 50 50 7 1 B
+X BOOT0 94 -200 -450 200 R 50 50 7 1 I
+ENDDRAW
+ENDDEF
+#
 # TCXO_DFAS11
 #
 DEF TCXO_DFAS11 X 0 40 Y Y 1 F N
--- a/fpgna.pro
+++ b/fpgna.pro
@ -1,4 +1,4 @@
-update=Mon 15 Feb 2016 06:12:25 PM CET
+update=Tue 16 Feb 2016 12:07:24 PM CET
 version=1
 last_client=kicad
 [pcbnew]
@ -63,3 +63,4 @@ LibName31=lattice/lattice
 LibName32=power/pmic
 LibName33=libs/specific-powersyms
 LibName34=power/regulators
+LibName35=stm/stm32f4
--- a/fpgna.sch
+++ b/fpgna.sch
@ -33,12 +33,13 @@ LIBS:lattice
 LIBS:pmic
 LIBS:specific-powersyms
 LIBS:regulators
+LIBS:stm32f4
 LIBS:fpgna-cache
 EELAYER 25 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
-Sheet 1 3
+Sheet 1 4
 Title "FPGna"
 Date ""
 Rev ""
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 F1 "debug.sch" 60
 $EndSheet
+$Sheet
+S 7250 1100 2050 2150
+U 56C43C85
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+F1 "FSMC.sch" 60
+$EndSheet
 $EndSCHEMATC
--- a/power.sch
+++ b/power.sch