SDRAM schematic + first layout try

This commit is contained in:
Markus Koch 2016-02-19 11:53:31 +01:00
parent f46704f400
commit 9eb3271030
12 changed files with 3876 additions and 2224 deletions

1
.gitignore vendored
View File

@ -2,3 +2,4 @@ shimatta-libs
*.bak *.bak
*.bck *.bck
*.kicad_pcb-bak *.kicad_pcb-bak
_saved*

144
FSMC.sch
View File

@ -35,12 +35,13 @@ LIBS:specific-powersyms
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LIBS:itead-displays LIBS:itead-displays
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@ -35,12 +35,13 @@ LIBS:specific-powersyms
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@ -35,12 +35,13 @@ LIBS:specific-powersyms
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View File

@ -1,3 +1,4 @@
(fp_lib_table (fp_lib_table
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View File

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X DQ8 42 -200 -900 200 R 50 50 2 1 B
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X WE 16 -200 -600 200 R 50 50 3 1 I I
X CAS 17 -200 -500 200 R 50 50 3 1 I I
X CKE 37 -200 -200 200 R 50 50 3 1 I
X RAS 18 -200 -400 200 R 50 50 3 1 I I
X CLK 38 -200 -100 200 R 50 50 3 1 I C
X CS 19 -200 -300 200 R 50 50 3 1 I I
X DQMH 39 750 -100 200 L 50 50 3 1 I
S 0 0 550 -300 4 1 0 f
X NC 40 -200 -200 200 R 50 50 4 1 N
X NC 36 -200 -100 200 R 50 50 4 1 N
ENDDRAW
ENDDEF
#
# ITDB02-3.2WD # ITDB02-3.2WD
# #
DEF ITDB02-3.2WD U 0 40 Y Y 5 L N DEF ITDB02-3.2WD U 0 40 Y Y 5 L N

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1357
fpgna.net

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@ -1,4 +1,4 @@
update=Mi 17 Feb 2016 20:01:19 CET update=Fri 19 Feb 2016 08:35:36 AM CET
version=1 version=1
last_client=kicad last_client=kicad
[pcbnew] [pcbnew]
@ -65,3 +65,4 @@ LibName33=libs/specific-powersyms
LibName34=power/regulators LibName34=power/regulators
LibName35=stm/stm32f4 LibName35=stm/stm32f4
LibName36=shields/itead-displays LibName36=shields/itead-displays
LibName37=memory/ram

View File

@ -35,12 +35,13 @@ LIBS:specific-powersyms
LIBS:regulators LIBS:regulators
LIBS:stm32f4 LIBS:stm32f4
LIBS:itead-displays LIBS:itead-displays
LIBS:ram
LIBS:fpgna-cache LIBS:fpgna-cache
EELAYER 25 0 EELAYER 25 0
EELAYER END EELAYER END
$Descr A4 11693 8268 $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 1 5 Sheet 1 6
Title "FPGna" Title "FPGna"
Date "" Date ""
Rev "" Rev ""
@ -91,4 +92,10 @@ F1 "display.sch" 60
$EndSheet $EndSheet
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B5 RAM\nB3 Display B5 RAM\nB3 Display
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F1 "sdram.sch" 60
$EndSheet
$EndSCHEMATC $EndSCHEMATC

1706
power.sch

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745
sdram.sch Normal file
View File

@ -0,0 +1,745 @@
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:Oscillators
LIBS:lattice
LIBS:pmic
LIBS:specific-powersyms
LIBS:regulators
LIBS:stm32f4
LIBS:itead-displays
LIBS:ram
LIBS:fpgna-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
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U 2 1 56C6F7AD
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F 0 "U7" H 3575 2787 60 0000 C CNN
F 1 "IS42S16800F" H 3575 2681 60 0000 C CNN
F 2 "smd:TSOP-54" H 3300 2600 60 0001 C CNN
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2 3300 2600
1 0 0 -1
$EndComp
$Comp
L IS42S16800F U7
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3 1300 2750
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$EndComp
$Comp
L IS42S16800F U7
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DQ4
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DQ5
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DQ6
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DQ7
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DQ8
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DQ9
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DQ10
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DQ11
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DQ12
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DQ13
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$Comp
L LFXP2-5E-6TN144C U?
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F 4 "1.0" H 5750 3550 60 0001 C CNN "Version"
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4 9400 2400
1 0 0 -1
$EndComp
$Comp
L LFXP2-5E-6TN144C U?
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AR Path="/56C43C85/56C7D396" Ref="U?" Part="5"
AR Path="/56C6F777/56C7D396" Ref="U3" Part="5"
F 0 "U3" H 6800 3237 60 0000 C CNN
F 1 "LFXP2-5E-6TN144C" H 6800 3131 60 0000 C CNN
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1 0 0 -1
$EndComp
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
4050 2900 4300 2900
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Wire Wire Line
4050 3100 4300 3100
Wire Wire Line
4050 3200 4300 3200
Wire Wire Line
4050 3300 4300 3300
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Wire Wire Line
4050 3500 4300 3500
Wire Wire Line
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Wire Wire Line
4050 3700 4300 3700
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
6150 3100 5850 3100
Wire Wire Line
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Wire Wire Line
6150 3300 5850 3300
Wire Wire Line
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Wire Wire Line
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Text Label 7800 2500 2 60 ~ 0
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
8750 2700 8500 2700
Wire Wire Line
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Wire Wire Line
8750 2900 8500 2900
Wire Wire Line
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8750 3100 8500 3100
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U 1 1 56C80517
P 5750 4100
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F 1 "100n" H 5800 4000 50 0000 L CNN
F 2 "" H 5788 3950 50 0001 C CNN
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1 5750 4100
-1 0 0 -1
$EndComp
$Comp
L C C?
U 1 1 56C8051E
P 5550 4100
F 0 "C?" H 5600 4200 50 0000 L CNN
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1 5550 4100
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
U 1 1 56C80525
P 6100 4400
F 0 "#PWR?" H 6100 4150 50 0001 C CNN
F 1 "GND" H 6108 4226 50 0000 C CNN
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F 3 "" H 6100 4400 50 0000 C CNN
1 6100 4400
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
U 1 1 56C8052B
P 5900 4400
F 0 "#PWR?" H 5900 4150 50 0001 C CNN
F 1 "GND" H 5908 4226 50 0000 C CNN
F 2 "" H 5900 4400 50 0000 C CNN
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1 5900 4400
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
U 1 1 56C80531
P 5650 4400
F 0 "#PWR?" H 5650 4150 50 0001 C CNN
F 1 "GND" H 5658 4226 50 0000 C CNN
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1 5650 4400
-1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
6100 4100 6150 4100
Wire Wire Line
6150 4000 5900 4000
Wire Wire Line
5900 4000 5900 4400
Wire Wire Line
5650 4400 5650 4250
Connection ~ 5650 4250
$Comp
L VFPGA33 #PWR?
U 1 1 56C8053D
P 5550 3850
F 0 "#PWR?" H 5550 3700 50 0001 C CNN
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1 5550 3850
-1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR?
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P 5750 3750
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1 5750 3750
-1 0 0 -1
$EndComp
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Connection ~ 5550 3900
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Wire Wire Line
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$Comp
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1 8350 4200
-1 0 0 -1
$EndComp
$Comp
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1 8150 4200
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
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1 8700 4500
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
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1 8500 4500
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
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1 8250 4500
-1 0 0 -1
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Wire Wire Line
8700 4200 8750 4200
Wire Wire Line
8750 4100 8500 4100
Wire Wire Line
8500 4100 8500 4500
Wire Wire Line
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Connection ~ 8250 4350
$Comp
L VFPGA33 #PWR?
U 1 1 56C807B6
P 8150 3950
F 0 "#PWR?" H 8150 3800 50 0001 C CNN
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1 8150 3950
-1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR?
U 1 1 56C807BC
P 8350 3850
F 0 "#PWR?" H 8350 3700 50 0001 C CNN
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1 8350 3850
-1 0 0 -1
$EndComp
Wire Wire Line
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Connection ~ 8150 4000
Wire Wire Line
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Wire Wire Line
8350 3850 8350 4050
Wire Wire Line
8150 4000 8750 4000
Wire Wire Line
8750 3900 8350 3900
Connection ~ 8350 3900
$Comp
L C C?
U 1 1 56C80907
P 7700 4200
F 0 "C?" H 7750 4300 50 0000 L CNN
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1 7700 4200
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
U 1 1 56C8090E
P 7500 4400
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F 3 "" H 7500 4400 50 0000 C CNN
1 7500 4400
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
U 1 1 56C80914
P 7700 4400
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1 7700 4400
-1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
7700 4000 7450 4000
Wire Wire Line
7500 4400 7500 4100
Wire Wire Line
7500 4100 7450 4100
Wire Wire Line
7700 4400 7700 4350
$Comp
L VFPGA33 #PWR?
U 1 1 56C8091F
P 7700 3750
F 0 "#PWR?" H 7700 3600 50 0001 C CNN
F 1 "VFPGA33" H 7718 3924 50 0000 C CNN
F 2 "" H 7700 3750 50 0000 C CNN
F 3 "" H 7700 3750 50 0000 C CNN
1 7700 3750
-1 0 0 -1
$EndComp
Connection ~ 7700 4000
$Comp
L C C?
U 1 1 56C80AD2
P 10300 4300
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F 3 "" H 10300 4300 50 0000 C CNN
1 10300 4300
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
U 1 1 56C80AD8
P 10100 4500
F 0 "#PWR?" H 10100 4250 50 0001 C CNN
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F 3 "" H 10100 4500 50 0000 C CNN
1 10100 4500
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
U 1 1 56C80ADE
P 10300 4500
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1 10300 4500
-1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
10300 4100 10050 4100
Wire Wire Line
10100 4500 10100 4200
Wire Wire Line
10100 4200 10050 4200
Wire Wire Line
10300 4500 10300 4450
$Comp
L VFPGA33 #PWR?
U 1 1 56C80AE9
P 10300 3850
F 0 "#PWR?" H 10300 3700 50 0001 C CNN
F 1 "VFPGA33" H 10318 4024 50 0000 C CNN
F 2 "" H 10300 3850 50 0000 C CNN
F 3 "" H 10300 3850 50 0000 C CNN
1 10300 3850
-1 0 0 -1
$EndComp
Connection ~ 10300 4100
$EndSCHEMATC