2018-04-30 09:08:47 +02:00
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[Device]
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Family=machxo2
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PartType=LCMXO2-1200HC
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PartName=LCMXO2-1200HC-5SG32C
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SpeedGrade=5
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Package=QFN32
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OperatingCondition=COM
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Status=S
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[IP]
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VendorName=Lattice Semiconductor Corporation
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CoreType=LPM
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CoreStatus=Demo
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CoreName=RAM_DP_TRUE
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CoreRevision=7.5
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ModuleName=gram0
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SourceFormat=VHDL
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ParameterFileVersion=1.0
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2020-05-10 20:47:47 +02:00
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Date=05/10/2020
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Time=13:18:44
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2018-04-30 09:08:47 +02:00
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[Parameters]
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Verilog=0
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VHDL=1
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EDIF=1
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Destination=Synplicity
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Expression=BusA(0 to 7)
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Order=Big Endian [MSB:LSB]
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IO=0
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RAddress=7000
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RData=9
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WAddress=7000
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WData=9
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ROutputEn=1
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RClockEn=0
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WOutputEn=1
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WClockEn=0
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enByte=0
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ByteSize=8
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Optimization=Speed
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Reset=Sync
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Reset1=Sync
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Init=mem
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2020-05-10 20:47:47 +02:00
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MemFile=/home/markus/projects/cross-discipline/lw35-upgrade/display/tools/splash.mem
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2018-04-30 09:08:47 +02:00
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MemFormat=bin
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EnECC=0
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Pipeline=0
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WriteA=Normal
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WriteB=Normal
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init_data=0
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[FilesGenerated]
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2020-05-10 20:47:47 +02:00
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/home/markus/projects/cross-discipline/lw35-upgrade/display/tools/splash.mem=mem
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2018-04-30 09:08:47 +02:00
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[Command]
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2020-05-10 20:47:47 +02:00
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cmd_line= -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-1200HC -aaddr_width 13 -widtha 9 -baddr_width 13 -widthb 9 -anum_words 7000 -bnum_words 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/cross-discipline/lw35-upgrade/display/tools/splash.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL
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