Add display driver

2018-04-30 09:08:47 +02:00 · 2018-04-30 09:08:47 +02:00 · 468275ed05
commit 468275ed05
61 changed files with 12070 additions and 0 deletions
--- a/.gitignore
+++ b/.gitignore
@ -0,0 +1 @@
+doc
--- a/README.MD
+++ b/README.MD
@ -0,0 +1,4 @@
+# Brother LW-35 Modernization
+Drivers, firmware and tools used in my LW-35 electronic typewriter modernization.
+
+Documentation coming soon-ish.
--- a/display/avr/.gitignore
+++ b/display/avr/.gitignore
@ -0,0 +1,2 @@
+*.hex
+*.o
--- a/display/avr/Makefile
+++ b/display/avr/Makefile
@ -0,0 +1,20 @@
+MCU=atmega328p
+CFLAGS=-g -Wall -mcall-prologues -mmcu=$(MCU) -Os -DF_CPU=16000000
+LDFLAGS=-Wl,-gc-sections -Wl,-relax
+CC=avr-gcc
+TARGET=main
+OBJECT_FILES=main.o
+
+all: $(TARGET).hex
+
+clean:
+	rm -f *.o *.hex *.obj *.hex
+
+%.hex: %.obj
+	avr-objcopy -R .eeprom -O ihex $< $@
+
+%.obj: $(OBJECT_FILES)
+	$(CC) $(CFLAGS) $(OBJECT_FILES) $(LDFLAGS) -o $@
+
+program: $(TARGET).hex
+	avrdude -p $(MCU) -P /dev/ttyUSB1 -c arduino -b 57600  -U flash:w:$(TARGET).hex
--- a/display/avr/main.c
+++ b/display/avr/main.c
@ -0,0 +1,73 @@
+#include <avr/io.h>
+#include <util/delay.h>
+#include <stdlib.h>
+
+#define LMG6202_DATA_PORT PORTD
+#define LMG6202_CONTROL_PORT PORTD
+
+#define LMG6202_PIN_CP (1 << 4)
+#define LMG6202_PIN_LD (1 << 5)
+#define LMG6202_PIN_DR (1 << 6)
+#define LMG6202_PIN_DF (1 << 7)
+
+int main()
+{
+	int i;
+	int col = 0;
+	uint16_t it = 0;
+	
+	UCSR0B = 0x00;
+	DDRD = 0xff;
+	PORTD = 0xff;
+	
+	_delay_ms(500);
+				
+	while (1) {
+		// VSYNC pulse
+		if (col == 1) {
+			LMG6202_CONTROL_PORT |= LMG6202_PIN_DR;
+			LMG6202_CONTROL_PORT ^= LMG6202_PIN_DF;
+//			_delay_us(1);
+		} else {
+			LMG6202_CONTROL_PORT &= ~LMG6202_PIN_DR;
+		}
+		
+		// Latch data
+		LMG6202_CONTROL_PORT |= LMG6202_PIN_LD;
+		asm("nop");asm("nop");asm("nop");
+		LMG6202_CONTROL_PORT &= ~LMG6202_PIN_LD;
+		
+		//LMG6202_CONTROL_PORT ^= LMG6202_PIN_DF;
+		_delay_us(1);
+		
+		for (i = 0; i < 120; ++i) {
+			LMG6202_CONTROL_PORT |= LMG6202_PIN_CP;
+			
+			if (it > 2500 && i > 60) {
+				//if (i == 0) {
+					LMG6202_DATA_PORT |= 15;
+				//}
+			} else {
+				LMG6202_DATA_PORT &= ~(15);
+			}
+			
+			//asm("nop");
+			LMG6202_CONTROL_PORT &= ~LMG6202_PIN_CP;
+			asm("nop");
+		}	
+		
+		LMG6202_DATA_PORT &= ~(15);
+//		LMG6202_CONTROL_PORT &= ~LMG6202_PIN_DR;
+		
+		if (col == 127) {
+			col = 0;			
+		} else {
+			col++;
+		}
+		if (it==5000) {
+			it = 0;
+		} else {
+			it++;
+		}
+	}
+}
--- a/display/fpga/.gitignore
+++ b/display/fpga/.gitignore
@ -0,0 +1,9 @@
+.settings
+diamond/impl1/
+*_tcr.dir
+*.html
+*.xml
+*.ccl
+*.ini
+.recovery
+*.log
--- a/display/fpga/.project
+++ b/display/fpga/.project
@ -0,0 +1,45 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>lmg6202</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
+		<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Common Libraries</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
+			<type>1</type>
+			<locationURI>sigasiresource:/vhdl/readme.txt</locationURI>
+		</link>
+		<link>
+			<name>Common Libraries/IEEE</name>
+			<type>2</type>
+			<locationURI>sigasiresource:/vhdl/93/IEEE</locationURI>
+		</link>
+		<link>
+			<name>Common Libraries/IEEE Synopsys</name>
+			<type>2</type>
+			<locationURI>sigasiresource:/vhdl/93/IEEE%20Synopsys</locationURI>
+		</link>
+		<link>
+			<name>Common Libraries/STD</name>
+			<type>2</type>
+			<locationURI>sigasiresource:/vhdl/93/STD</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
--- a/display/fpga/bench/bench_top.vhd
+++ b/display/fpga/bench/bench_top.vhd
@ -0,0 +1,120 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library design;
+use design.all;
+
+entity bench_top is
+end entity bench_top;
+
+architecture RTL of bench_top is
+	signal clk    : std_logic;
+	signal rst_hw : std_logic;
+
+	signal lcd_data : std_logic_vector(3 downto 0);
+	signal lcd_clp  : std_logic;
+	signal lcd_load : std_logic;
+	signal lcd_frp  : std_logic;
+	signal lcd_frmb : std_logic;
+
+	signal spi_cs_n : std_logic;
+	signal spi_sck  : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_miso : std_logic;
+
+begin
+	top_inst : entity design.top
+		port map(
+			spi_cs_n => spi_cs_n,
+			spi_sck  => spi_sck,
+			spi_mosi => spi_mosi,
+			spi_miso => spi_miso,
+			clk_hw   => clk,
+			rst_hw   => rst_hw,
+			lcd_data => lcd_data,
+			lcd_clp  => lcd_clp,
+			lcd_load => lcd_load,
+			lcd_frp  => lcd_frp,
+			lcd_frmb => lcd_frmb
+		);
+
+	clock_driver : process
+		constant period : time := (1 sec / 24000000);
+	begin
+		clk <= '0';
+		wait for period / 2;
+		clk <= '1';
+		wait for period / 2;
+	end process clock_driver;
+
+	test : process is
+	begin
+		rst_hw <= '0';
+		wait for 100 ns;
+		rst_hw <= '1';
+		wait;
+	end process test;
+	
+	spitest : process is
+		constant CPOL : std_logic := '0';
+		constant DEL : time  := 400 ns;
+		
+		procedure send_byte(data : std_logic_vector(7 downto 0)) is
+		
+		begin
+			for i in 7 downto 0 loop
+				spi_sck <= CPOL;
+				wait for DEL;
+				spi_mosi <= data(i);
+				spi_sck <= not CPOL;
+				wait for DEL;
+			end loop;
+		end procedure send_byte;
+		
+	begin
+		spi_cs_n <= '1';
+		spi_sck <= '0';
+		spi_mosi <= CPOL;
+		
+		wait until rst_hw = '1';
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		spi_cs_n <= '0';
+		wait for 400 ns;
+		send_byte(x"00");
+		send_byte(x"00");
+		send_byte(x"00");
+		
+		send_byte(x"AB");
+		send_byte(x"CD");
+		send_byte(x"55");
+		send_byte(x"AA");
+		send_byte(x"81");
+		
+		send_byte(x"2A");
+		send_byte(x"AB");
+		send_byte(x"BC");
+		send_byte(x"CF");
+		
+		send_byte(x"AB");
+		send_byte(x"CD");
+		send_byte(x"55");
+		send_byte(x"AA");
+		send_byte(x"81");
+		
+		send_byte(x"2A");
+		send_byte(x"AB");
+		send_byte(x"BC");
+		send_byte(x"CF");
+		
+		spi_cs_n <= '1';
+		
+		wait;
+	end process spitest;
+	
+
+end architecture RTL;
--- a/display/fpga/design/lmg6202.vhd
+++ b/display/fpga/design/lmg6202.vhd
@ -0,0 +1,189 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library ip;
+use ip.all;
+
+entity lmg6202 is
+	generic(
+		F_CLK     : natural;
+		LCD_F_CLP : natural := 2_000_000 -- Max 2.5 MHz atm (because fo t_lc)
+	);
+	port(
+		-- System signals
+		clk       : in  std_logic;
+		rst       : in  std_logic;      --
+
+		-- Interface signals
+		addr_in   : in  std_logic_vector(12 downto 0);
+		data_in   : in  std_logic_vector(8 downto 0);
+		data_we   : in  std_logic;
+		data_out  : out std_logic_vector(8 downto 0);
+		vsync_out : out std_logic;      -- Strobed when resetting to the top left
+		vsync_in  : in  std_logic;      -- Reset renderer to the top left corner
+
+		-- LCD hardware signals
+		lcd_data  : out std_logic_vector(3 downto 0);
+		lcd_clp   : out std_logic;
+		lcd_load  : out std_logic;
+		lcd_frp   : out std_logic;
+		lcd_frmb  : out std_logic
+	);
+end entity lmg6202;
+
+architecture RTL of lmg6202 is
+	constant DISPLAY_WIDTH_PX  : natural := 480;
+	constant DISPLAY_HEIGHT_PX : natural := 128;
+
+	constant DISPLAY_WIDTH  : natural := DISPLAY_WIDTH_PX / 4;
+	constant DISPLAY_HEIGHT : natural := DISPLAY_HEIGHT_PX;
+
+	-- CLP Gen
+	constant CLP_CNT_MAX : integer := F_CLK / LCD_F_CLP / 2 - 1;
+	signal clp_cnt       : integer range 0 to CLP_CNT_MAX;
+	signal clp_falling   : std_logic;
+
+	signal row : integer range 0 to DISPLAY_HEIGHT - 1;
+	signal col : integer range 0 to DISPLAY_WIDTH - 1;
+
+	signal renderer_addr     : unsigned(12 downto 0);
+	signal renderer_data     : std_logic_vector(8 downto 0);
+	signal additional_nibble : std_logic_vector(3 downto 0);
+	signal cached_nibble     : std_logic_vector(3 downto 0);
+	signal clp_rising        : std_logic;
+	signal step_cnt          : unsigned(3 downto 0);
+
+begin
+	gram0_inst : entity ip.gram0
+		port map(
+			DataInA  => data_in,
+			DataInB  => (others => '0'),
+			AddressA => addr_in,
+			AddressB => std_logic_vector(renderer_addr),
+			ClockA   => clk,
+			ClockB   => clk,
+			ClockEnA => '1',
+			ClockEnB => '1',
+			WrA      => data_we,
+			WrB      => '0',
+			ResetA   => rst,
+			ResetB   => rst,
+			QA       => data_out,
+			QB       => renderer_data
+		);
+
+	renderer : process(clk, rst) is
+		procedure reset_renderer is
+
+		begin
+			row           <= 0;
+			col           <= 0;
+			renderer_addr <= (others => '0');
+			step_cnt      <= (others => '0');
+			vsync_out     <= '1';
+		end procedure reset_renderer;
+
+	begin
+		if (rst = '1') then
+			additional_nibble <= (others => '0');
+			cached_nibble     <= (others => '0');
+			lcd_load          <= '0';
+			lcd_frp           <= '0';
+			lcd_frmb          <= '0';
+			lcd_data          <= (others => '0');
+			reset_renderer;
+
+		elsif (rising_edge(clk)) then
+			vsync_out <= '0';
+
+			if (clp_falling = '1') then
+				if (col = DISPLAY_WIDTH - 1) then
+					col      <= 0;
+					lcd_load <= '1';
+
+					if (row = 0) then
+						lcd_frp  <= '1';
+						lcd_frmb <= not lcd_frmb;
+					else
+						lcd_frp <= '0';
+					end if;
+
+					if (row = DISPLAY_HEIGHT - 1) then
+						reset_renderer;
+					else
+						row <= row + 1;
+					end if;
+				else
+					col <= col + 1;
+				end if;
+			end if;
+
+			if (clp_rising = '1') then
+				lcd_load <= '0';
+
+				step_cnt <= step_cnt + 1;
+				if (step_cnt = 8) then
+					step_cnt <= (others => '0');
+					lcd_data <= additional_nibble;
+
+				elsif (step_cnt(0) = '0') then
+					renderer_addr <= renderer_addr + 1;
+
+					lcd_data          <= renderer_data(8 downto 5);
+					cached_nibble     <= renderer_data(4 downto 1);
+					additional_nibble <= additional_nibble(2 downto 0) & renderer_data(0);
+
+				else
+					lcd_data <= cached_nibble;
+				end if;
+
+				-- DEBUG BEGIN
+				--				lcd_data <= (others => '0');
+				--				if (col = 0) then
+				--					lcd_data <= x"8";
+				--				end if;
+				--				if (col = DISPLAY_WIDTH - 1) then
+				--					lcd_data <= x"1";
+				--				end if;
+				--				if (row = 0 or row = DISPLAY_HEIGHT - 1) then
+				--					lcd_data <= (others => '1');
+				--				end if;
+				-- DEBUG END
+			end if;
+
+			if (vsync_in = '1') then
+				reset_renderer;
+			end if;
+		end if;
+	end process renderer;
+
+	cpgen : process(clk, rst) is
+	begin
+		if (rst = '1') then
+			clp_cnt     <= CLP_CNT_MAX;
+			lcd_clp     <= '0';
+			clp_falling <= '0';
+			clp_rising  <= '0';
+
+		elsif (rising_edge(clk)) then
+			clp_falling <= '0';
+			clp_rising  <= '0';
+
+			if (clp_cnt = 0) then
+				lcd_clp <= not lcd_clp;
+				clp_cnt <= CLP_CNT_MAX;
+			else
+				if (clp_cnt = 1) then
+					if (lcd_clp = '1') then
+						clp_falling <= '1';
+					else
+						clp_rising <= '1';
+					end if;
+				end if;
+				clp_cnt <= clp_cnt - 1;
+			end if;
+		end if;
+	end process cpgen;
+
+end architecture RTL;
--- a/display/fpga/design/spi_if.vhd
+++ b/display/fpga/design/spi_if.vhd
@ -0,0 +1,165 @@
+-- FIXME: synchronizer
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity spi_if is
+	port(
+		clk      : in    std_logic;
+		rst      : in    std_logic;     --
+
+		-- Local memory IF
+		addr     : out   std_logic_vector(12 downto 0);
+		data_in  : in    std_logic_vector(8 downto 0);
+		data_we  : out   std_logic;
+		data_out : out   std_logic_vector(8 downto 0); --
+
+		-- Other control signals
+		vsync_rq : out   std_logic;     --
+
+		-- SPI IF
+		spi_cs_n : in    std_logic;     -- SPI chip select, active low
+		spi_sck  : in    std_logic;     -- SPI clock
+		spi_mosi : in    std_logic;     -- SPI data input
+		spi_miso : inout std_logic      -- SPI data output
+	);
+end entity spi_if;
+
+architecture RTL of spi_if is
+	signal spi_sck_last : std_logic;
+	signal sr_in        : std_logic_vector(3 downto 0);
+	signal sr_out       : std_logic_vector(3 downto 0);
+	signal bit_cnt      : unsigned(1 downto 0);
+
+	signal rx_stb : std_logic;
+
+	type state_t is (IDLE, ADDRESS, DATA, FLUSH, LOCK);
+	signal state    : state_t;
+	signal word_cnt : unsigned(3 downto 0);
+
+	signal cache_nor   : std_logic_vector(2 * 4 * 4 - 1 downto 0);
+	signal cache_extra : std_logic_vector(4 - 1 downto 0);
+
+begin
+	spi_receiver : process(clk, rst) is
+	begin
+		if (rst = '1') then
+			spi_miso     <= 'Z';
+			bit_cnt      <= (others => '0');
+			sr_in        <= (others => '0');
+			rx_stb       <= '0';
+			spi_sck_last <= '0';
+
+		elsif (rising_edge(clk)) then
+			rx_stb       <= '0';
+			spi_sck_last <= spi_sck;
+
+			if (spi_cs_n = '0') then
+				if (spi_sck = '1' and spi_sck_last = '0') then -- rising edge of SPI clock, write
+					sr_in   <= sr_in(sr_in'high - 1 downto 0) & spi_mosi;
+					bit_cnt <= bit_cnt + 1;
+					if (bit_cnt = 3) then
+						rx_stb <= '1';
+					end if;
+				elsif (spi_sck = '0' and spi_sck_last = '1') then -- falling edge of SPI clock, read
+
+				end if;
+
+			else
+				spi_miso <= 'Z';
+				bit_cnt  <= (others => '0');
+				sr_in    <= (others => '0');
+			end if;
+
+		end if;
+	end process spi_receiver;
+
+	proc : process(clk, rst) is
+	begin
+		if (rst = '1') then
+			addr        <= (others => '0');
+			data_we     <= '0';
+			word_cnt    <= (others => '0');
+			cache_nor   <= (others => '0');
+			cache_extra <= (others => '0');
+			vsync_rq    <= '0';
+			state       <= IDLE;
+
+		elsif (rising_edge(clk)) then
+			data_we  <= '0';
+			vsync_rq <= '0';
+
+			if (spi_cs_n = '0') then
+
+				case state is
+					when IDLE =>
+						if (rx_stb = '1') then
+							word_cnt <= word_cnt + 1;
+							if (word_cnt = 1) then
+								if (sr_in = x"0") then -- Start at addr
+									state    <= ADDRESS;
+									word_cnt <= (others => '0');
+									addr <= (others => '0');
+								elsif (sr_in = x"1") then -- Continue
+									state    <= DATA;
+									word_cnt <= (others => '0');
+								else
+									state <= LOCK;
+								end if;
+							end if;
+						end if;
+
+					when ADDRESS =>
+						if (rx_stb = '1') then
+							addr     <= addr(addr'high - 4 downto 0) & sr_in;
+							word_cnt <= word_cnt + 1;
+							if (word_cnt = 3) then
+								state    <= DATA;
+								word_cnt <= (others => '0');
+							end if;
+						end if;
+
+					when DATA =>
+						if (data_we = '1') then -- If we came from FLUSH
+							addr <= std_logic_vector(unsigned(addr) + 1);
+						end if;
+						if (rx_stb = '1') then
+							word_cnt <= word_cnt + 1;
+							if (word_cnt = 8) then
+								cache_extra <= sr_in;
+								state       <= FLUSH;
+								word_cnt    <= (others => '0');
+								data_we     <= '1';
+
+							else
+								cache_nor <= cache_nor(cache_nor'high - 4 downto 0) & sr_in;
+							end if;
+						end if;
+
+					when FLUSH =>
+						addr        <= std_logic_vector(unsigned(addr) + 1);
+						cache_nor   <= cache_nor(cache_nor'high - 8 downto 0) & x"00";
+						cache_extra <= cache_extra(cache_extra'high - 1 downto 0) & '0';
+						data_we     <= '1';
+						word_cnt    <= word_cnt + 1;
+						if (word_cnt = 2) then
+							state    <= DATA;
+							word_cnt <= (others => '0');
+						end if;
+
+					when LOCK =>
+						vsync_rq <= '1';
+						null;
+				end case;
+			else
+				state    <= IDLE;
+				--addr     <= (others => '0');
+				data_we  <= '0';
+				word_cnt <= (others => '0');
+			end if;
+		end if;
+	end process proc;
+	data_out <= cache_nor(cache_nor'high downto cache_nor'high - 7) & cache_extra(cache_extra'high);
+
+end architecture RTL;
--- a/display/fpga/design/top.vhd
+++ b/display/fpga/design/top.vhd
@ -0,0 +1,170 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library generics;
+library ip;
+
+entity top is
+	port(
+		-- System ports
+		clk_hw    : in    std_logic;    -- System clock @ F_CLK
+		rst_hw    : in    std_logic;    -- Asynchronous, active low reset
+
+		-- SPI IF
+		spi_cs_n  : in    std_logic;    -- SPI chip select, active low
+		spi_sck   : in    std_logic;    -- SPI clock
+		spi_mosi  : in    std_logic;    -- SPI data input
+		spi_miso  : inout std_logic;    -- SPI data output
+
+		-- LEDs
+		led_red   : out   std_logic;
+		led_green : out   std_logic;
+		-- LCD connection
+		lcd_data  : out   std_logic_vector(3 downto 0);
+		lcd_clp   : out   std_logic;
+		lcd_load  : out   std_logic;
+		lcd_frp   : out   std_logic;
+		lcd_frmb  : out   std_logic
+	);
+end entity top;
+
+architecture RTL of top is
+	constant F_CLK : natural := 96_000_000;
+
+	signal clk : std_logic;
+	signal rst : std_logic;
+	signal pll_lock : std_logic;
+
+	signal addr_in  : std_logic_vector(12 downto 0);
+	signal data_in  : std_logic_vector(8 downto 0);
+	signal data_we  : std_logic;
+	signal data_out : std_logic_vector(8 downto 0);
+	signal vsync    : std_logic;
+	signal vsync_rq : std_logic;
+
+	signal spi_cs_n_sync : std_logic;
+	signal spi_sck_sync  : std_logic;
+
+
+begin
+	pll0_inst : entity ip.pll0
+		port map(
+			CLKI  => clk_hw,
+			CLKOP => clk,
+			LOCK  => pll_lock
+		);
+
+	rst_sync : process(clk, rst_hw, pll_lock) is
+		variable tmp : std_logic;
+
+	begin
+		if (rst_hw = '0' or pll_lock = '0') then
+			rst <= '1';
+			tmp := '1';
+
+		elsif rising_edge(clk) then
+			rst <= tmp;
+			tmp := '0';
+		end if;
+	end process rst_sync;
+
+	lmg6202_inst : entity work.lmg6202
+		generic map(
+			F_CLK => F_CLK
+		)
+		port map(
+			clk       => clk,
+			rst       => rst,
+			addr_in   => addr_in,
+			data_in   => data_in,
+			data_we   => data_we,
+			data_out  => data_out,
+			vsync_out => vsync,
+			vsync_in  => vsync_rq,
+			lcd_data  => lcd_data,
+			lcd_clp   => lcd_clp,
+			lcd_load  => lcd_load,
+			lcd_frp   => lcd_frp,
+			lcd_frmb  => lcd_frmb
+		);
+
+	spi_if_inst : entity work.spi_if
+		port map(
+			clk      => clk,
+			rst      => rst,
+			addr     => addr_in,
+			data_in  => data_out,
+			data_we  => data_we,
+			data_out => data_in,
+			vsync_rq => vsync_rq,
+			spi_cs_n => spi_cs_n_sync,
+			spi_sck  => spi_sck_sync,
+			spi_mosi => spi_mosi,
+			spi_miso => spi_miso
+		);
+
+	synchronizer0_inst : entity generics.synchronizer
+		generic map(
+			INIT => '1'
+		)
+		port map(
+			clk  => clk,
+			rst  => rst,
+			din  => spi_cs_n,
+			dout => spi_cs_n_sync
+		);
+
+	synchronizer1_inst : entity generics.synchronizer
+		generic map(
+			INIT => '0'
+		)
+		port map(
+			clk  => clk,
+			rst  => rst,
+			din  => spi_sck,
+			dout => spi_sck_sync
+		);
+
+	debug : process(clk, rst) is
+		constant CMAX : integer := F_CLK / 32;
+		variable cnt  : integer range 0 to CMAX;
+		variable cnt2  : integer range 0 to CMAX;
+
+	begin
+		if rst = '1' then
+			led_red <= '1';
+			led_green <= '1';
+
+			cnt := CMAX;
+			cnt2 := CMAX;
+
+		elsif (rising_edge(clk)) then
+			if (cnt > 0) then
+				cnt := cnt - 1;
+			end if;
+			if (cnt2 > 0) then
+				cnt2 := cnt2 - 1;
+			end if;
+			
+			if (data_we = '1') then -- green
+				cnt := CMAX;
+			end if;
+			if (vsync_rq = '1') then -- red
+				cnt2 := CMAX;
+			end if;
+			
+			if (cnt = 0) then
+				led_green <= '1';
+			else
+				led_green <= '0';
+			end if;
+			if (cnt2 = 0) then
+				led_red <= '1';
+			else
+				led_red <= '0';
+			end if;
+		end if;
+	end process debug;
+
+end architecture RTL;
--- a/display/fpga/diamond/lmg6202.ldf
+++ b/display/fpga/diamond/lmg6202.ldf
@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="lmg6202" device="LCMXO2-1200HC-5SG32C" default_implementation="impl1">
+    <Options/>
+    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="design.top" top="design.top"/>
+        <Source name="../ip/gram0/gram0.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="../design/lmg6202.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="design"/>
+        </Source>
+        <Source name="../design/top.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="design" top_module="design.top"/>
+        </Source>
+        <Source name="../ip/gram0/gram0.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="ip"/>
+        </Source>
+        <Source name="../design/spi_if.vhd" type="VHDL" type_short="VHDL">
+            <Options lib="design"/>
+        </Source>
+        <Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
+            <Options/>
+        </Source>
+        <Source name="lmg6202.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="lmg62021.sty"/>
+</BaliProject>
--- a/display/fpga/diamond/lmg6202.lpf
+++ b/display/fpga/diamond/lmg6202.lpf
@ -0,0 +1,33 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "clk_hw" SITE "28" ;
+LOCATE COMP "rst_hw" SITE "23" ;
+IOBUF PORT "rst_hw" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+LOCATE COMP "lcd_data[0]" SITE "14" ;
+LOCATE COMP "lcd_data[1]" SITE "13" ;
+LOCATE COMP "lcd_clp" SITE "10" ;
+LOCATE COMP "lcd_load" SITE "9" ;
+LOCATE COMP "lcd_frp" SITE "8" ;
+LOCATE COMP "lcd_frmb" SITE "5" ;
+IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
+IOBUF PORT "clk_hw" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "lcd_clp" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "lcd_data[0]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "lcd_data[1]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "lcd_data[2]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "lcd_data[3]" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "lcd_frmb" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "lcd_frp" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "lcd_load" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "lcd_data[2]" SITE "12" ;
+LOCATE COMP "lcd_data[3]" SITE "11" ;
+FREQUENCY NET "clk_hw_c" 12.000000 MHz ;
+IOBUF PORT "spi_cs_n" IO_TYPE=LVCMOS33 PULLMODE=UP ;
+IOBUF PORT "spi_sck" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
+IOBUF PORT "spi_miso" IO_TYPE=LVCMOS33 ;
+LOCATE COMP "spi_cs_n" SITE "27" ;
+LOCATE COMP "spi_mosi" SITE "17" ;
+LOCATE COMP "spi_sck" SITE "16" ;
+LOCATE COMP "spi_miso" SITE "25" ;
+LOCATE COMP "led_green" SITE "21" ;
+LOCATE COMP "led_red" SITE "20" ;
--- a/display/fpga/diamond/lmg62021.sty
+++ b/display/fpga/diamond/lmg62021.sty
@ -0,0 +1,205 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+    <Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
+    <Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_BD_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_BD_ParSearchPath" value="" time="0"/>
+    <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
+    <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
+    <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
+    <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
+    <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
+    <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
+    <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
+    <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
+    <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
+    <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
+    <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_NoHeader" value="False" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
+    <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
+    <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
+    <Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
+    <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
+    <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
+    <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
+    <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
+    <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
+    <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
+    <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
+    <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_LST_CarryChain" value="True" time="0"/>
+    <Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
+    <Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
+    <Property name="PROP_LST_DSPUtil" value="100" time="0"/>
+    <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
+    <Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
+    <Property name="PROP_LST_EBRUtil" value="100" time="0"/>
+    <Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
+    <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
+    <Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
+    <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
+    <Property name="PROP_LST_EdfMemPath" value="" time="0"/>
+    <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
+    <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
+    <Property name="PROP_LST_IOInsertion" value="True" time="0"/>
+    <Property name="PROP_LST_InterFileDump" value="False" time="0"/>
+    <Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
+    <Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
+    <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
+    <Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
+    <Property name="PROP_LST_PropagatConst" value="True" time="0"/>
+    <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
+    <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
+    <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_LST_ResourceShare" value="True" time="0"/>
+    <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
+    <Property name="PROP_LST_UseLPF" value="True" time="0"/>
+    <Property name="PROP_LST_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
+    <Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
+    <Property name="PROP_MAP_GuideFileMapDes" value="" time="0"/>
+    <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
+    <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
+    <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
+    <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
+    <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
+    <Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
+    <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
+    <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
+    <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
+    <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
+    <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
+    <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
+    <Property name="PROP_PARSTA_FullName" value="False" time="0"/>
+    <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
+    <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
+    <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
+    <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
+    <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
+    <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
+    <Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
+    <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
+    <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
+    <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
+    <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+    <Property name="PROP_PAR_ParGuideRepMatch" value="False" time="0"/>
+    <Property name="PROP_PAR_ParMatchFact" value="" time="0"/>
+    <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
+    <Property name="PROP_PAR_ParNCDGuideFile" value="" time="0"/>
+    <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
+    <Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
+    <Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
+    <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
+    <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
+    <Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
+    <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
+    <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
+    <Property name="PROP_PAR_StopZero" value="False" time="0"/>
+    <Property name="PROP_PAR_parHold" value="On" time="0"/>
+    <Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
+    <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
+    <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
+    <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
+    <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
+    <Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
+    <Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
+    <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
+    <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
+    <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
+    <Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
+    <Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
+    <Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
+    <Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
+    <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
+    <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfArea" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
+    <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
+    <Property name="PROP_SYN_EdfFrequency" value="" time="0"/>
+    <Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
+    <Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
+    <Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
+    <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
+    <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
+    <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
+    <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
+    <Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
+    <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
+    <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
+    <Property name="PROP_SYN_UseLPF" value="True" time="0"/>
+    <Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
+    <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
+    <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
+    <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
+    <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
+    <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
+    <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
+    <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
+    <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
+    <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
+</Strategy>
--- a/display/fpga/generics/ram.vhd
+++ b/display/fpga/generics/ram.vhd
@ -0,0 +1,74 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram is
+	generic(
+		WIDTH : natural := 9;
+		DEPTH : natural := 10
+	);
+	port(
+		clk        : in  std_logic;
+		rst        : in  std_logic;     --
+
+		a_addr_in  : in  std_logic_vector(DEPTH - 1 downto 0);
+		a_data_in  : in  std_logic_vector(WIDTH - 1 downto 0);
+		a_data_out : out std_logic_vector(WIDTH - 1 downto 0);
+		a_we       : in  std_logic;     --
+
+		b_addr_in  : in  std_logic_vector(DEPTH - 1 downto 0);
+		b_data_out : out std_logic_vector(WIDTH - 1 downto 0)
+	);
+end entity ram;
+
+architecture RTL of ram is
+	type memory_t is array (0 to 2**DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
+	signal memory : memory_t;
+
+begin
+	mem_p : process(clk, rst) is
+	begin
+		if (rst = '1') then
+			a_data_out <= (others => '0');
+			b_data_out <= (others => '0');
+
+--			memory(0) <= "111100001";
+--			memory(1) <= "100101001";
+--			memory(2) <= "000000000";
+--			memory(3) <= "101010100";
+--			
+--			memory(4) <= "111111111";
+--			memory(5) <= "000000000";
+--			memory(6) <= "000000000";
+--			memory(7) <= "000000000";
+----			
+----			memory(0) <= "111111111";
+----			memory(1) <= "111111111";
+----			memory(2) <= "111111111";
+----			memory(3) <= "111111111";
+----			memory(4) <= "111111111";
+----			memory(5) <= "111111111";
+----			memory(6) <= "111111111";
+----			memory(7) <= "111111111";
+--
+--			memory(0) <= "101010101";
+--			memory(1) <= "101010100";
+--			memory(2) <= "101010101";
+--			memory(3) <= "101010100";
+--			
+--			memory(4) <= "101010101";
+--			memory(5) <= "101010100";
+--			memory(6) <= "101010101";
+--			memory(7) <= "101010100";
+			
+		elsif (rising_edge(clk)) then
+			a_data_out <= memory(to_integer(unsigned(a_addr_in)));
+			b_data_out <= memory(to_integer(unsigned(b_addr_in)));
+
+			if (a_we = '1') then
+				memory(to_integer(unsigned(a_addr_in))) <= a_data_in;
+			end if;
+		end if;
+	end process mem_p;
+
+end architecture RTL;
--- a/display/fpga/generics/synchronizer.vhd
+++ b/display/fpga/generics/synchronizer.vhd
@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity synchronizer is
+	generic(
+		INIT : std_logic := '0'
+	);
+	port(
+		clk  : in  std_logic;
+		rst  : in  std_logic;
+		din  : in  std_logic;
+		dout : out std_logic
+	);
+end entity synchronizer;
+
+architecture RTL of synchronizer is
+	signal tmp : std_logic_vector(1 downto 0);
+
+begin
+	sync_p : process(clk, rst) is
+	begin
+		if (rst = '1') then
+			tmp  <= (others => INIT);
+			dout <= INIT;
+
+		elsif (rising_edge(clk)) then
+			tmp  <= tmp(0) & din;
+			dout <= tmp(1);
+		end if;
+	end process sync_p;
+
+end architecture RTL;
--- a/display/fpga/gtkwave/bench_top.gtkw
+++ b/display/fpga/gtkwave/bench_top.gtkw
@ -0,0 +1,77 @@
+[*]
+[*] GTKWave Analyzer v3.3.89 (w)1999-2018 BSI
+[*] Tue Apr 24 15:18:59 2018
+[*]
+[dumpfile] "/tmp/SigasiCompileCache8922493919830884349/lmg6202/mentor/bench_top.ghw"
+[dumpfile_mtime] "Tue Apr 24 15:18:24 2018"
+[dumpfile_size] 343957
+[savefile] "/home/markus/projects/workspaceSigasi/lmg6202/gtkwave/bench_top.gtkw"
+[timestart] 10940000000
+[size] 1920 1043
+[pos] -1 -1
+*-33.419907 48604165889 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.bench_top.
+[treeopen] top.bench_top.top_inst.
+[treeopen] top.bench_top.top_inst.lmg6202_inst.
+[treeopen] top.bench_top.top_inst.lmg6202_inst.gram0_inst.
+[treeopen] top.bench_top.top_inst.lmg6202_inst.gram0_inst.ram_inst.
+[treeopen] top.bench_top.top_inst.spi_if_inst.
+[sst_width] 233
+[signals_width] 262
+[sst_expanded] 1
+[sst_vpaned_height] 309
+@28
+top.bench_top.top_inst.lmg6202_inst.lcd_clp
+top.bench_top.top_inst.lmg6202_inst.lcd_load
+top.bench_top.top_inst.lmg6202_inst.lcd_frp
+top.bench_top.top_inst.lmg6202_inst.lcd_frmb
+@22
+#{top.bench_top.top_inst.lmg6202_inst.lcd_data[3:0]} top.bench_top.top_inst.lmg6202_inst.lcd_data[3] top.bench_top.top_inst.lmg6202_inst.lcd_data[2] top.bench_top.top_inst.lmg6202_inst.lcd_data[1] top.bench_top.top_inst.lmg6202_inst.lcd_data[0]
+#{top.bench_top.top_inst.lmg6202_inst.additional_nibble[3:0]} top.bench_top.top_inst.lmg6202_inst.additional_nibble[3] top.bench_top.top_inst.lmg6202_inst.additional_nibble[2] top.bench_top.top_inst.lmg6202_inst.additional_nibble[1] top.bench_top.top_inst.lmg6202_inst.additional_nibble[0]
+#{top.bench_top.top_inst.lmg6202_inst.renderer_data[8:0]} top.bench_top.top_inst.lmg6202_inst.renderer_data[8] top.bench_top.top_inst.lmg6202_inst.renderer_data[7] top.bench_top.top_inst.lmg6202_inst.renderer_data[6] top.bench_top.top_inst.lmg6202_inst.renderer_data[5] top.bench_top.top_inst.lmg6202_inst.renderer_data[4] top.bench_top.top_inst.lmg6202_inst.renderer_data[3] top.bench_top.top_inst.lmg6202_inst.renderer_data[2] top.bench_top.top_inst.lmg6202_inst.renderer_data[1] top.bench_top.top_inst.lmg6202_inst.renderer_data[0]
+#{top.bench_top.top_inst.lmg6202_inst.renderer_addr[12:0]} top.bench_top.top_inst.lmg6202_inst.renderer_addr[12] top.bench_top.top_inst.lmg6202_inst.renderer_addr[11] top.bench_top.top_inst.lmg6202_inst.renderer_addr[10] top.bench_top.top_inst.lmg6202_inst.renderer_addr[9] top.bench_top.top_inst.lmg6202_inst.renderer_addr[8] top.bench_top.top_inst.lmg6202_inst.renderer_addr[7] top.bench_top.top_inst.lmg6202_inst.renderer_addr[6] top.bench_top.top_inst.lmg6202_inst.renderer_addr[5] top.bench_top.top_inst.lmg6202_inst.renderer_addr[4] top.bench_top.top_inst.lmg6202_inst.renderer_addr[3] top.bench_top.top_inst.lmg6202_inst.renderer_addr[2] top.bench_top.top_inst.lmg6202_inst.renderer_addr[1] top.bench_top.top_inst.lmg6202_inst.renderer_addr[0]
+#{top.bench_top.top_inst.lmg6202_inst.data_out[3:0]} top.bench_top.top_inst.lmg6202_inst.data_out[3] top.bench_top.top_inst.lmg6202_inst.data_out[2] top.bench_top.top_inst.lmg6202_inst.data_out[1] top.bench_top.top_inst.lmg6202_inst.data_out[0]
+#{top.bench_top.top_inst.lmg6202_inst.data_in[3:0]} top.bench_top.top_inst.lmg6202_inst.data_in[3] top.bench_top.top_inst.lmg6202_inst.data_in[2] top.bench_top.top_inst.lmg6202_inst.data_in[1] top.bench_top.top_inst.lmg6202_inst.data_in[0]
+#{top.bench_top.top_inst.lmg6202_inst.addr_in[12:0]} top.bench_top.top_inst.lmg6202_inst.addr_in[12] top.bench_top.top_inst.lmg6202_inst.addr_in[11] top.bench_top.top_inst.lmg6202_inst.addr_in[10] top.bench_top.top_inst.lmg6202_inst.addr_in[9] top.bench_top.top_inst.lmg6202_inst.addr_in[8] top.bench_top.top_inst.lmg6202_inst.addr_in[7] top.bench_top.top_inst.lmg6202_inst.addr_in[6] top.bench_top.top_inst.lmg6202_inst.addr_in[5] top.bench_top.top_inst.lmg6202_inst.addr_in[4] top.bench_top.top_inst.lmg6202_inst.addr_in[3] top.bench_top.top_inst.lmg6202_inst.addr_in[2] top.bench_top.top_inst.lmg6202_inst.addr_in[1] top.bench_top.top_inst.lmg6202_inst.addr_in[0]
+@28
+top.bench_top.top_inst.lmg6202_inst.clp_rising
+@420
+top.bench_top.top_inst.lmg6202_inst.col
+top.bench_top.top_inst.lmg6202_inst.row
+@28
+top.bench_top.top_inst.lmg6202_inst.clp_falling
+@420
+top.bench_top.top_inst.lmg6202_inst.clp_cnt
+@28
+top.bench_top.top_inst.lmg6202_inst.data_we
+top.bench_top.top_inst.lmg6202_inst.rst
+top.bench_top.top_inst.lmg6202_inst.clk
+@200
+-
+@420
+top.bench_top.top_inst.spi_if_inst.state
+@28
+top.bench_top.top_inst.spi_if_inst.spi_sck_last
+top.bench_top.top_inst.spi_if_inst.spi_miso
+top.bench_top.top_inst.spi_if_inst.spi_mosi
+top.bench_top.top_inst.spi_if_inst.spi_sck
+top.bench_top.top_inst.spi_if_inst.spi_cs_n
+top.bench_top.top_inst.spi_if_inst.vsync_rq
+top.bench_top.top_inst.spi_if_inst.data_we
+top.bench_top.top_inst.spi_if_inst.rst
+top.bench_top.top_inst.spi_if_inst.clk
+@22
+#{top.bench_top.top_inst.spi_if_inst.addr[12:0]} top.bench_top.top_inst.spi_if_inst.addr[12] top.bench_top.top_inst.spi_if_inst.addr[11] top.bench_top.top_inst.spi_if_inst.addr[10] top.bench_top.top_inst.spi_if_inst.addr[9] top.bench_top.top_inst.spi_if_inst.addr[8] top.bench_top.top_inst.spi_if_inst.addr[7] top.bench_top.top_inst.spi_if_inst.addr[6] top.bench_top.top_inst.spi_if_inst.addr[5] top.bench_top.top_inst.spi_if_inst.addr[4] top.bench_top.top_inst.spi_if_inst.addr[3] top.bench_top.top_inst.spi_if_inst.addr[2] top.bench_top.top_inst.spi_if_inst.addr[1] top.bench_top.top_inst.spi_if_inst.addr[0]
+#{top.bench_top.top_inst.spi_if_inst.sr_in[3:0]} top.bench_top.top_inst.spi_if_inst.sr_in[3] top.bench_top.top_inst.spi_if_inst.sr_in[2] top.bench_top.top_inst.spi_if_inst.sr_in[1] top.bench_top.top_inst.spi_if_inst.sr_in[0]
+@28
+top.bench_top.top_inst.spi_if_inst.rx_stb
+@22
+#{top.bench_top.top_inst.spi_if_inst.word_cnt[3:0]} top.bench_top.top_inst.spi_if_inst.word_cnt[3] top.bench_top.top_inst.spi_if_inst.word_cnt[2] top.bench_top.top_inst.spi_if_inst.word_cnt[1] top.bench_top.top_inst.spi_if_inst.word_cnt[0]
+#{top.bench_top.top_inst.spi_if_inst.data_out[8:0]} top.bench_top.top_inst.spi_if_inst.data_out[8] top.bench_top.top_inst.spi_if_inst.data_out[7] top.bench_top.top_inst.spi_if_inst.data_out[6] top.bench_top.top_inst.spi_if_inst.data_out[5] top.bench_top.top_inst.spi_if_inst.data_out[4] top.bench_top.top_inst.spi_if_inst.data_out[3] top.bench_top.top_inst.spi_if_inst.data_out[2] top.bench_top.top_inst.spi_if_inst.data_out[1] top.bench_top.top_inst.spi_if_inst.data_out[0]
+#{top.bench_top.top_inst.spi_if_inst.cache_extra[3:0]} top.bench_top.top_inst.spi_if_inst.cache_extra[3] top.bench_top.top_inst.spi_if_inst.cache_extra[2] top.bench_top.top_inst.spi_if_inst.cache_extra[1] top.bench_top.top_inst.spi_if_inst.cache_extra[0]
+#{top.bench_top.top_inst.spi_if_inst.cache_nor[31:0]} top.bench_top.top_inst.spi_if_inst.cache_nor[31] top.bench_top.top_inst.spi_if_inst.cache_nor[30] top.bench_top.top_inst.spi_if_inst.cache_nor[29] top.bench_top.top_inst.spi_if_inst.cache_nor[28] top.bench_top.top_inst.spi_if_inst.cache_nor[27] top.bench_top.top_inst.spi_if_inst.cache_nor[26] top.bench_top.top_inst.spi_if_inst.cache_nor[25] top.bench_top.top_inst.spi_if_inst.cache_nor[24] top.bench_top.top_inst.spi_if_inst.cache_nor[23] top.bench_top.top_inst.spi_if_inst.cache_nor[22] top.bench_top.top_inst.spi_if_inst.cache_nor[21] top.bench_top.top_inst.spi_if_inst.cache_nor[20] top.bench_top.top_inst.spi_if_inst.cache_nor[19] top.bench_top.top_inst.spi_if_inst.cache_nor[18] top.bench_top.top_inst.spi_if_inst.cache_nor[17] top.bench_top.top_inst.spi_if_inst.cache_nor[16] top.bench_top.top_inst.spi_if_inst.cache_nor[15] top.bench_top.top_inst.spi_if_inst.cache_nor[14] top.bench_top.top_inst.spi_if_inst.cache_nor[13] top.bench_top.top_inst.spi_if_inst.cache_nor[12] top.bench_top.top_inst.spi_if_inst.cache_nor[11] top.bench_top.top_inst.spi_if_inst.cache_nor[10] top.bench_top.top_inst.spi_if_inst.cache_nor[9] top.bench_top.top_inst.spi_if_inst.cache_nor[8] top.bench_top.top_inst.spi_if_inst.cache_nor[7] top.bench_top.top_inst.spi_if_inst.cache_nor[6] top.bench_top.top_inst.spi_if_inst.cache_nor[5] top.bench_top.top_inst.spi_if_inst.cache_nor[4] top.bench_top.top_inst.spi_if_inst.cache_nor[3] top.bench_top.top_inst.spi_if_inst.cache_nor[2] top.bench_top.top_inst.spi_if_inst.cache_nor[1] top.bench_top.top_inst.spi_if_inst.cache_nor[0]
+@23
+#{top.bench_top.top_inst.spi_if_inst.data_out[8:0]} top.bench_top.top_inst.spi_if_inst.data_out[8] top.bench_top.top_inst.spi_if_inst.data_out[7] top.bench_top.top_inst.spi_if_inst.data_out[6] top.bench_top.top_inst.spi_if_inst.data_out[5] top.bench_top.top_inst.spi_if_inst.data_out[4] top.bench_top.top_inst.spi_if_inst.data_out[3] top.bench_top.top_inst.spi_if_inst.data_out[2] top.bench_top.top_inst.spi_if_inst.data_out[1] top.bench_top.top_inst.spi_if_inst.data_out[0]
+[pattern_trace] 1
+[pattern_trace] 0
--- a/display/fpga/ip/gram0/._Real_._Math_.vhd
+++ b/display/fpga/ip/gram0/._Real_._Math_.vhd
--- a/display/fpga/ip/gram0/generate_core.tcl
+++ b/display/fpga/ip/gram0/generate_core.tcl
@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "gram0"
+set lang "vhdl"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "xo2c00"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
--- a/display/fpga/ip/gram0/generate_ngd.tcl
+++ b/display/fpga/ip/gram0/generate_ngd.tcl
@ -0,0 +1,74 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "gram0"
+set Para(Module) "RAM_DP_TRUE"
+set Para(libname) machxo2
+set Para(arch_name) xo2c00
+set Para(PartType) "LCMXO2-1200HC"
+
+set Para(tech_syn) machxo2
+set Para(tech_cae) machxo2
+set Para(Package) "QFN32"
+set Para(SpeedGrade) "5"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
--- a/display/fpga/ip/gram0/gram0.cst
+++ b/display/fpga/ip/gram0/gram0.cst
@ -0,0 +1,3 @@
+Date=04/22/2018
+Time=17:34:06
+
--- a/display/fpga/ip/gram0/gram0.edn
+++ b/display/fpga/ip/gram0/gram0.edn
--- a/display/fpga/ip/gram0/gram0.ipx
+++ b/display/fpga/ip/gram0/gram0.ipx
@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="gram0" module="gram0" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 04 22 11:42:01.314" version="7.5" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="" type="mem" modified="2018 04 22 11:42:01.000"/>
+		<File name="gram0.lpc" type="lpc" modified="2018 04 22 11:42:00.000"/>
+		<File name="gram0.vhd" type="top_level_vhdl" modified="2018 04 22 11:42:00.000"/>
+		<File name="gram0_tmpl.vhd" type="template_vhdl" modified="2018 04 22 11:42:00.000"/>
+		<File name="tb_gram0_tmpl.vhd" type="testbench_vhdl" modified="2018 04 22 11:42:00.000"/>
+  </Package>
+</DiamondModule>
--- a/display/fpga/ip/gram0/gram0.jhd
+++ b/display/fpga/ip/gram0/gram0.jhd
@ -0,0 +1,87 @@
+MODULE gram0 DEFIN gram0.vhd
+	SUBMODULE MUX81
+		INSTANCE mux_0
+	SUBMODULE VLO
+		INSTANCE scuba_vlo_inst
+	SUBMODULE MUX81
+		INSTANCE mux_1
+	SUBMODULE MUX81
+		INSTANCE mux_2
+	SUBMODULE MUX81
+		INSTANCE mux_3
+	SUBMODULE MUX81
+		INSTANCE mux_4
+	SUBMODULE MUX81
+		INSTANCE mux_5
+	SUBMODULE MUX81
+		INSTANCE mux_6
+	SUBMODULE MUX81
+		INSTANCE mux_7
+	SUBMODULE MUX81
+		INSTANCE mux_8
+	SUBMODULE MUX81
+		INSTANCE mux_9
+	SUBMODULE MUX81
+		INSTANCE mux_10
+	SUBMODULE MUX81
+		INSTANCE mux_11
+	SUBMODULE MUX81
+		INSTANCE mux_12
+	SUBMODULE MUX81
+		INSTANCE mux_13
+	SUBMODULE MUX81
+		INSTANCE mux_14
+	SUBMODULE MUX81
+		INSTANCE mux_15
+	SUBMODULE MUX81
+		INSTANCE mux_16
+	SUBMODULE MUX81
+		INSTANCE mux_17
+	SUBMODULE FD1P3DX
+		INSTANCE FF_0
+	SUBMODULE FD1P3DX
+		INSTANCE FF_1
+	SUBMODULE FD1P3DX
+		INSTANCE FF_2
+	SUBMODULE FD1P3DX
+		INSTANCE FF_3
+	SUBMODULE FD1P3DX
+		INSTANCE FF_4
+	SUBMODULE FD1P3DX
+		INSTANCE FF_5
+	SUBMODULE FD1P3DX
+		INSTANCE FF_6
+	SUBMODULE FD1P3DX
+		INSTANCE FF_7
+	SUBMODULE FD1P3DX
+		INSTANCE FF_8
+	SUBMODULE FD1P3DX
+		INSTANCE FF_9
+	SUBMODULE FD1P3DX
+		INSTANCE FF_10
+	SUBMODULE FD1P3DX
+		INSTANCE FF_11
+	SUBMODULE DP8KC
+		INSTANCE gram0_6_0_0
+	SUBMODULE VHI
+		INSTANCE scuba_vhi_inst
+	SUBMODULE DP8KC
+		INSTANCE gram0_5_0_1
+	SUBMODULE DP8KC
+		INSTANCE gram0_4_0_2
+	SUBMODULE DP8KC
+		INSTANCE gram0_3_0_3
+	SUBMODULE DP8KC
+		INSTANCE gram0_2_0_4
+	SUBMODULE DP8KC
+		INSTANCE gram0_1_0_5
+	SUBMODULE DP8KC
+		INSTANCE gram0_0_0_6
+	SUBMODULE AND2
+		INSTANCE AND2_t0
+	SUBMODULE INV
+		INSTANCE INV_0
+	SUBMODULE AND2
+		INSTANCE AND2_t1
+	SUBMODULE INV
+		INSTANCE INV_1
--- a/display/fpga/ip/gram0/gram0.lpc
+++ b/display/fpga/ip/gram0/gram0.lpc
@ -0,0 +1,56 @@
+[Device]
+Family=machxo2
+PartType=LCMXO2-1200HC
+PartName=LCMXO2-1200HC-5SG32C
+SpeedGrade=5
+Package=QFN32
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP_TRUE
+CoreRevision=7.5
+ModuleName=gram0
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/22/2018
+Time=17:34:06
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=7000
+RData=9
+WAddress=7000
+WData=9
+ROutputEn=1
+RClockEn=0
+WOutputEn=1
+WClockEn=0
+enByte=0
+ByteSize=8
+Optimization=Speed
+Reset=Sync
+Reset1=Sync
+Init=mem
+MemFile=/home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem
+MemFormat=bin
+EnECC=0
+Pipeline=0
+WriteA=Normal
+WriteB=Normal
+init_data=0
+
+[FilesGenerated]
+/home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem=mem
+
+[Command]
+cmd_line= -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-1200HC -aaddr_width 13 -widtha 9 -baddr_width 13 -widthb 9 -anum_words 7000 -bnum_words 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL
--- a/display/fpga/ip/gram0/gram0.naf
+++ b/display/fpga/ip/gram0/gram0.naf
@ -0,0 +1,70 @@
+DataInA[8]  i
+DataInA[7]  i
+DataInA[6]  i
+DataInA[5]  i
+DataInA[4]  i
+DataInA[3]  i
+DataInA[2]  i
+DataInA[1]  i
+DataInA[0]  i
+DataInB[8]  i
+DataInB[7]  i
+DataInB[6]  i
+DataInB[5]  i
+DataInB[4]  i
+DataInB[3]  i
+DataInB[2]  i
+DataInB[1]  i
+DataInB[0]  i
+AddressA[12]  i
+AddressA[11]  i
+AddressA[10]  i
+AddressA[9]  i
+AddressA[8]  i
+AddressA[7]  i
+AddressA[6]  i
+AddressA[5]  i
+AddressA[4]  i
+AddressA[3]  i
+AddressA[2]  i
+AddressA[1]  i
+AddressA[0]  i
+AddressB[12]  i
+AddressB[11]  i
+AddressB[10]  i
+AddressB[9]  i
+AddressB[8]  i
+AddressB[7]  i
+AddressB[6]  i
+AddressB[5]  i
+AddressB[4]  i
+AddressB[3]  i
+AddressB[2]  i
+AddressB[1]  i
+AddressB[0]  i
+ClockA  i
+ClockB  i
+ClockEnA  i
+ClockEnB  i
+WrA  i
+WrB  i
+ResetA  i
+ResetB  i
+QA[8]  o
+QA[7]  o
+QA[6]  o
+QA[5]  o
+QA[4]  o
+QA[3]  o
+QA[2]  o
+QA[1]  o
+QA[0]  o
+QB[8]  o
+QB[7]  o
+QB[6]  o
+QB[5]  o
+QB[4]  o
+QB[3]  o
+QB[2]  o
+QB[1]  o
+QB[0]  o
--- a/display/fpga/ip/gram0/gram0.sort
+++ b/display/fpga/ip/gram0/gram0.sort
@ -0,0 +1 @@
+gram0.vhd
--- a/display/fpga/ip/gram0/gram0.srp
+++ b/display/fpga/ip/gram0/gram0.srp
@ -0,0 +1,35 @@
+SCUBA, Version Diamond (64-bit) 3.10.0.111.2
+Sun Apr 22 17:34:06 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-1200HC -aaddr_width 13 -widtha 9 -baddr_width 13 -widthb 9 -anum_words 7000 -bnum_words 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL 
+    Circuit name     : gram0
+    Module type      : RAM_DP_TRUE
+    Module Version   : 7.5
+    Ports            : 
+	Inputs       : DataInA[8:0], DataInB[8:0], AddressA[12:0], AddressB[12:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
+	Outputs      : QA[8:0], QB[8:0]
+    I/O buffer       : not inserted
+    Memory file      : /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem
+    EDIF output      : gram0.edn
+    VHDL output      : gram0.vhd
+    VHDL template    : gram0_tmpl.vhd
+    VHDL testbench    : tb_gram0_tmpl.vhd
+    VHDL purpose     : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : gram0.srp
+    Element Usage    :
+           AND2 : 2
+        FD1P3DX : 12
+            INV : 2
+          MUX81 : 18
+          DP8KC : 7
+    Estimated Resource Usage:
+            LUT : 38
+            EBR : 7
+            Reg : 12
--- a/display/fpga/ip/gram0/gram0.sym
+++ b/display/fpga/ip/gram0/gram0.sym
--- a/display/fpga/ip/gram0/gram0.vhd
+++ b/display/fpga/ip/gram0/gram0.vhd
@ -0,0 +1,943 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
+-- Module  Version: 7.5
+--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 11 -rp 1010 -data_width 9 -rdata_width 9 -num_rows 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL 
+
+-- Sun Apr 22 17:34:06 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO2;
+use MACHXO2.components.all;
+-- synopsys translate_on
+
+entity gram0 is
+    port (
+        DataInA: in  std_logic_vector(8 downto 0); 
+        DataInB: in  std_logic_vector(8 downto 0); 
+        AddressA: in  std_logic_vector(12 downto 0); 
+        AddressB: in  std_logic_vector(12 downto 0); 
+        ClockA: in  std_logic; 
+        ClockB: in  std_logic; 
+        ClockEnA: in  std_logic; 
+        ClockEnB: in  std_logic; 
+        WrA: in  std_logic; 
+        WrB: in  std_logic; 
+        ResetA: in  std_logic; 
+        ResetB: in  std_logic; 
+        QA: out  std_logic_vector(8 downto 0); 
+        QB: out  std_logic_vector(8 downto 0));
+end gram0;
+
+architecture Structure of gram0 is
+
+    -- internal signal declarations
+    signal wren0_inv: std_logic;
+    signal wren1_inv: std_logic;
+    signal scuba_vhi: std_logic;
+    signal wren0_inv_g: std_logic;
+    signal addr010_ff: std_logic;
+    signal addr011_ff: std_logic;
+    signal addr012_ff: std_logic;
+    signal wren1_inv_g: std_logic;
+    signal addr110_ff: std_logic;
+    signal addr111_ff: std_logic;
+    signal addr112_ff: std_logic;
+    signal mdout0_6_0: std_logic;
+    signal mdout0_5_0: std_logic;
+    signal mdout0_4_0: std_logic;
+    signal mdout0_3_0: std_logic;
+    signal mdout0_2_0: std_logic;
+    signal mdout0_1_0: std_logic;
+    signal mdout0_0_0: std_logic;
+    signal mdout0_6_1: std_logic;
+    signal mdout0_5_1: std_logic;
+    signal mdout0_4_1: std_logic;
+    signal mdout0_3_1: std_logic;
+    signal mdout0_2_1: std_logic;
+    signal mdout0_1_1: std_logic;
+    signal mdout0_0_1: std_logic;
+    signal mdout0_6_2: std_logic;
+    signal mdout0_5_2: std_logic;
+    signal mdout0_4_2: std_logic;
+    signal mdout0_3_2: std_logic;
+    signal mdout0_2_2: std_logic;
+    signal mdout0_1_2: std_logic;
+    signal mdout0_0_2: std_logic;
+    signal mdout0_6_3: std_logic;
+    signal mdout0_5_3: std_logic;
+    signal mdout0_4_3: std_logic;
+    signal mdout0_3_3: std_logic;
+    signal mdout0_2_3: std_logic;
+    signal mdout0_1_3: std_logic;
+    signal mdout0_0_3: std_logic;
+    signal mdout0_6_4: std_logic;
+    signal mdout0_5_4: std_logic;
+    signal mdout0_4_4: std_logic;
+    signal mdout0_3_4: std_logic;
+    signal mdout0_2_4: std_logic;
+    signal mdout0_1_4: std_logic;
+    signal mdout0_0_4: std_logic;
+    signal mdout0_6_5: std_logic;
+    signal mdout0_5_5: std_logic;
+    signal mdout0_4_5: std_logic;
+    signal mdout0_3_5: std_logic;
+    signal mdout0_2_5: std_logic;
+    signal mdout0_1_5: std_logic;
+    signal mdout0_0_5: std_logic;
+    signal mdout0_6_6: std_logic;
+    signal mdout0_5_6: std_logic;
+    signal mdout0_4_6: std_logic;
+    signal mdout0_3_6: std_logic;
+    signal mdout0_2_6: std_logic;
+    signal mdout0_1_6: std_logic;
+    signal mdout0_0_6: std_logic;
+    signal mdout0_6_7: std_logic;
+    signal mdout0_5_7: std_logic;
+    signal mdout0_4_7: std_logic;
+    signal mdout0_3_7: std_logic;
+    signal mdout0_2_7: std_logic;
+    signal mdout0_1_7: std_logic;
+    signal mdout0_0_7: std_logic;
+    signal addr012_ff2: std_logic;
+    signal addr011_ff2: std_logic;
+    signal addr010_ff2: std_logic;
+    signal mdout0_6_8: std_logic;
+    signal mdout0_5_8: std_logic;
+    signal mdout0_4_8: std_logic;
+    signal mdout0_3_8: std_logic;
+    signal mdout0_2_8: std_logic;
+    signal mdout0_1_8: std_logic;
+    signal mdout0_0_8: std_logic;
+    signal mdout1_6_0: std_logic;
+    signal mdout1_5_0: std_logic;
+    signal mdout1_4_0: std_logic;
+    signal mdout1_3_0: std_logic;
+    signal mdout1_2_0: std_logic;
+    signal mdout1_1_0: std_logic;
+    signal mdout1_0_0: std_logic;
+    signal mdout1_6_1: std_logic;
+    signal mdout1_5_1: std_logic;
+    signal mdout1_4_1: std_logic;
+    signal mdout1_3_1: std_logic;
+    signal mdout1_2_1: std_logic;
+    signal mdout1_1_1: std_logic;
+    signal mdout1_0_1: std_logic;
+    signal mdout1_6_2: std_logic;
+    signal mdout1_5_2: std_logic;
+    signal mdout1_4_2: std_logic;
+    signal mdout1_3_2: std_logic;
+    signal mdout1_2_2: std_logic;
+    signal mdout1_1_2: std_logic;
+    signal mdout1_0_2: std_logic;
+    signal mdout1_6_3: std_logic;
+    signal mdout1_5_3: std_logic;
+    signal mdout1_4_3: std_logic;
+    signal mdout1_3_3: std_logic;
+    signal mdout1_2_3: std_logic;
+    signal mdout1_1_3: std_logic;
+    signal mdout1_0_3: std_logic;
+    signal mdout1_6_4: std_logic;
+    signal mdout1_5_4: std_logic;
+    signal mdout1_4_4: std_logic;
+    signal mdout1_3_4: std_logic;
+    signal mdout1_2_4: std_logic;
+    signal mdout1_1_4: std_logic;
+    signal mdout1_0_4: std_logic;
+    signal mdout1_6_5: std_logic;
+    signal mdout1_5_5: std_logic;
+    signal mdout1_4_5: std_logic;
+    signal mdout1_3_5: std_logic;
+    signal mdout1_2_5: std_logic;
+    signal mdout1_1_5: std_logic;
+    signal mdout1_0_5: std_logic;
+    signal mdout1_6_6: std_logic;
+    signal mdout1_5_6: std_logic;
+    signal mdout1_4_6: std_logic;
+    signal mdout1_3_6: std_logic;
+    signal mdout1_2_6: std_logic;
+    signal mdout1_1_6: std_logic;
+    signal mdout1_0_6: std_logic;
+    signal mdout1_6_7: std_logic;
+    signal mdout1_5_7: std_logic;
+    signal mdout1_4_7: std_logic;
+    signal mdout1_3_7: std_logic;
+    signal mdout1_2_7: std_logic;
+    signal mdout1_1_7: std_logic;
+    signal mdout1_0_7: std_logic;
+    signal addr112_ff2: std_logic;
+    signal addr111_ff2: std_logic;
+    signal addr110_ff2: std_logic;
+    signal scuba_vlo: std_logic;
+    signal mdout1_6_8: std_logic;
+    signal mdout1_5_8: std_logic;
+    signal mdout1_4_8: std_logic;
+    signal mdout1_3_8: std_logic;
+    signal mdout1_2_8: std_logic;
+    signal mdout1_1_8: std_logic;
+    signal mdout1_0_8: std_logic;
+
+    -- local component declarations
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component MUX81
+        port (D0: in  std_logic; D1: in  std_logic; D2: in  std_logic; 
+            D3: in  std_logic; D4: in  std_logic; D5: in  std_logic; 
+            D6: in  std_logic; D7: in  std_logic; SD1: in  std_logic; 
+            SD2: in  std_logic; SD3: in  std_logic; Z: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component DP8KC
+        generic (INIT_DATA : in String; INITVAL_1F : in String; 
+                INITVAL_1E : in String; INITVAL_1D : in String; 
+                INITVAL_1C : in String; INITVAL_1B : in String; 
+                INITVAL_1A : in String; INITVAL_19 : in String; 
+                INITVAL_18 : in String; INITVAL_17 : in String; 
+                INITVAL_16 : in String; INITVAL_15 : in String; 
+                INITVAL_14 : in String; INITVAL_13 : in String; 
+                INITVAL_12 : in String; INITVAL_11 : in String; 
+                INITVAL_10 : in String; INITVAL_0F : in String; 
+                INITVAL_0E : in String; INITVAL_0D : in String; 
+                INITVAL_0C : in String; INITVAL_0B : in String; 
+                INITVAL_0A : in String; INITVAL_09 : in String; 
+                INITVAL_08 : in String; INITVAL_07 : in String; 
+                INITVAL_06 : in String; INITVAL_05 : in String; 
+                INITVAL_04 : in String; INITVAL_03 : in String; 
+                INITVAL_02 : in String; INITVAL_01 : in String; 
+                INITVAL_00 : in String; ASYNC_RESET_RELEASE : in String; 
+                RESETMODE : in String; GSR : in String; 
+                WRITEMODE_B : in String; WRITEMODE_A : in String; 
+                CSDECODE_B : in String; CSDECODE_A : in String; 
+                REGMODE_B : in String; REGMODE_A : in String; 
+                DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+        port (DIA8: in  std_logic; DIA7: in  std_logic; 
+            DIA6: in  std_logic; DIA5: in  std_logic; 
+            DIA4: in  std_logic; DIA3: in  std_logic; 
+            DIA2: in  std_logic; DIA1: in  std_logic; 
+            DIA0: in  std_logic; ADA12: in  std_logic; 
+            ADA11: in  std_logic; ADA10: in  std_logic; 
+            ADA9: in  std_logic; ADA8: in  std_logic; 
+            ADA7: in  std_logic; ADA6: in  std_logic; 
+            ADA5: in  std_logic; ADA4: in  std_logic; 
+            ADA3: in  std_logic; ADA2: in  std_logic; 
+            ADA1: in  std_logic; ADA0: in  std_logic; CEA: in  std_logic; 
+            OCEA: in  std_logic; CLKA: in  std_logic; WEA: in  std_logic; 
+            CSA2: in  std_logic; CSA1: in  std_logic; 
+            CSA0: in  std_logic; RSTA: in  std_logic; 
+            DIB8: in  std_logic; DIB7: in  std_logic; 
+            DIB6: in  std_logic; DIB5: in  std_logic; 
+            DIB4: in  std_logic; DIB3: in  std_logic; 
+            DIB2: in  std_logic; DIB1: in  std_logic; 
+            DIB0: in  std_logic; ADB12: in  std_logic; 
+            ADB11: in  std_logic; ADB10: in  std_logic; 
+            ADB9: in  std_logic; ADB8: in  std_logic; 
+            ADB7: in  std_logic; ADB6: in  std_logic; 
+            ADB5: in  std_logic; ADB4: in  std_logic; 
+            ADB3: in  std_logic; ADB2: in  std_logic; 
+            ADB1: in  std_logic; ADB0: in  std_logic; CEB: in  std_logic; 
+            OCEB: in  std_logic; CLKB: in  std_logic; WEB: in  std_logic; 
+            CSB2: in  std_logic; CSB1: in  std_logic; 
+            CSB0: in  std_logic; RSTB: in  std_logic; 
+            DOA8: out  std_logic; DOA7: out  std_logic; 
+            DOA6: out  std_logic; DOA5: out  std_logic; 
+            DOA4: out  std_logic; DOA3: out  std_logic; 
+            DOA2: out  std_logic; DOA1: out  std_logic; 
+            DOA0: out  std_logic; DOB8: out  std_logic; 
+            DOB7: out  std_logic; DOB6: out  std_logic; 
+            DOB5: out  std_logic; DOB4: out  std_logic; 
+            DOB3: out  std_logic; DOB2: out  std_logic; 
+            DOB1: out  std_logic; DOB0: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute GSR : string; 
+    attribute MEM_LPC_FILE of gram0_0_0_6 : label is "gram0.lpc";
+    attribute MEM_INIT_FILE of gram0_0_0_6 : label is "gram_init.mem";
+    attribute MEM_LPC_FILE of gram0_1_0_5 : label is "gram0.lpc";
+    attribute MEM_INIT_FILE of gram0_1_0_5 : label is "gram_init.mem";
+    attribute MEM_LPC_FILE of gram0_2_0_4 : label is "gram0.lpc";
+    attribute MEM_INIT_FILE of gram0_2_0_4 : label is "gram_init.mem";
+    attribute MEM_LPC_FILE of gram0_3_0_3 : label is "gram0.lpc";
+    attribute MEM_INIT_FILE of gram0_3_0_3 : label is "gram_init.mem";
+    attribute MEM_LPC_FILE of gram0_4_0_2 : label is "gram0.lpc";
+    attribute MEM_INIT_FILE of gram0_4_0_2 : label is "gram_init.mem";
+    attribute MEM_LPC_FILE of gram0_5_0_1 : label is "gram0.lpc";
+    attribute MEM_INIT_FILE of gram0_5_0_1 : label is "gram_init.mem";
+    attribute MEM_LPC_FILE of gram0_6_0_0 : label is "gram0.lpc";
+    attribute MEM_INIT_FILE of gram0_6_0_0 : label is "gram_init.mem";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    INV_1: INV
+        port map (A=>WrA, Z=>wren0_inv);
+
+    AND2_t1: AND2
+        port map (A=>wren0_inv, B=>ClockEnA, Z=>wren0_inv_g);
+
+    INV_0: INV
+        port map (A=>WrB, Z=>wren1_inv);
+
+    AND2_t0: AND2
+        port map (A=>wren1_inv, B=>ClockEnB, Z=>wren1_inv_g);
+
+    gram0_0_0_6: DP8KC
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA8=>DataInA(8), DIA7=>DataInA(7), DIA6=>DataInA(6), 
+            DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3), 
+            DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0), 
+            ADA12=>AddressA(9), ADA11=>AddressA(8), ADA10=>AddressA(7), 
+            ADA9=>AddressA(6), ADA8=>AddressA(5), ADA7=>AddressA(4), 
+            ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1), 
+            ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo, 
+            ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, 
+            WEA=>WrA, CSA2=>AddressA(12), CSA1=>AddressA(11), 
+            CSA0=>AddressA(10), RSTA=>ResetA, DIB8=>DataInB(8), 
+            DIB7=>DataInB(7), DIB6=>DataInB(6), DIB5=>DataInB(5), 
+            DIB4=>DataInB(4), DIB3=>DataInB(3), DIB2=>DataInB(2), 
+            DIB1=>DataInB(1), DIB0=>DataInB(0), ADB12=>AddressB(9), 
+            ADB11=>AddressB(8), ADB10=>AddressB(7), ADB9=>AddressB(6), 
+            ADB8=>AddressB(5), ADB7=>AddressB(4), ADB6=>AddressB(3), 
+            ADB5=>AddressB(2), ADB4=>AddressB(1), ADB3=>AddressB(0), 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vhi, 
+            CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, 
+            CSB2=>AddressB(12), CSB1=>AddressB(11), CSB0=>AddressB(10), 
+            RSTB=>ResetB, DOA8=>mdout0_0_8, DOA7=>mdout0_0_7, 
+            DOA6=>mdout0_0_6, DOA5=>mdout0_0_5, DOA4=>mdout0_0_4, 
+            DOA3=>mdout0_0_3, DOA2=>mdout0_0_2, DOA1=>mdout0_0_1, 
+            DOA0=>mdout0_0_0, DOB8=>mdout1_0_8, DOB7=>mdout1_0_7, 
+            DOB6=>mdout1_0_6, DOB5=>mdout1_0_5, DOB4=>mdout1_0_4, 
+            DOB3=>mdout1_0_3, DOB2=>mdout1_0_2, DOB1=>mdout1_0_1, 
+            DOB0=>mdout1_0_0);
+
+    gram0_1_0_5: DP8KC
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        INITVAL_1F=> "0x0020100201000003F07E001F83FDFE3FBFE3FDC03FEFF00201000000000000000000003FC1E00000", 
+        INITVAL_1E=> "0x001F03FC3E3F87E000003E0FE00000000003C1FE00000001FC3FE0F0020100000001C00FE01303FF", 
+        INITVAL_1D=> "0x3FFC13FFFF3C3FF3FE0F00000000000000000000001F03FC00000003F1FE03FC13FE07001803FC0E", 
+        INITVAL_1C=> "0x00000001003FE01002013F9FE0FC000000000000381FE00C003FDFF03FFD3FE0F3FFFF00E0100201", 
+        INITVAL_1B=> "0x00000001FC3FFFF3FFFF303FF3FFFF3FEFF003FD207FF3FFFF3FFFF07FFF3FFFF3FFFF00F813FFFF", 
+        INITVAL_1A=> "0x0020100000000003F83E001FC3FDFE3FDFE1FDE03FE7F0020100000000003FDFE3FDFE3FE1F3F3FF", 
+        INITVAL_19=> "0x3FFFF3FE033F83E3F1FE3FFFF3FFFF3FFFF3FDFF3FEFF003F93FE030020100000001C007E01383FF", 
+        INITVAL_18=> "0x3FFE13FFFF3C3FF3FE060000000000001E03FDFE3FFFF1FF813FFFF3FFFF003E13FF833FFFF3FFFF", 
+        INITVAL_17=> "0x3FFF73FFFF3FFFF3FE0F3F1FE03C0000000000003C1FE004003FDFF01FFF3FF0F3FFFF00E0100201", 
+        INITVAL_16=> "0x00000001FE3FFFF3FFFF383FF3FFFE3FE0F003FF307FF3FFFF3FFFF27FFF3FFFF3FFFF00F013FEFF", 
+        INITVAL_15=> "0x0000000000000003FC1E001FE3FCFE3FDFE0FDF03FE3F0020100000000003FDFE3FDFF3FE0F3FBFF", 
+        INITVAL_14=> "0x3FFFF07E013FC1E3F1FE3FFFF3FFFF3FFFE3FDFF3FE7F003F10FE010020100000001E003E013C3FF", 
+        INITVAL_13=> "0x1FFF13FFFF3F3FF3FC020000000000001F03FDFE3FFFF0FFC13FFFF3FEFF001E03FDC03FFFF3FFFF", 
+        INITVAL_12=> "0x3FFFB3FFFF3FFFF3FE073E1FE00C0000000000003C1FE000003FFFF21FFF3FF873FFFF0060100201", 
+        INITVAL_11=> "0x00000201FE3FFFF3FFFF383FF3FDFE03E01203FF383FF3FFFF3FFFF37FFF3FFFF3FFFF00F013FE3F", 
+        INITVAL_10=> "0x0000000000001003FC1E001FE3FC7E3FDFE0FDF93FE3F0020100000000003FDFE3FDFF3FE073FBFF", 
+        INITVAL_0F=> "0x3FE3F002013FC1E3F9FF3FFFF3FFFF3FDFE3FFFF3FE3F003E103E010020100000001F001E013C3FF", 
+        INITVAL_0E=> "0x0FFF13FFFF3F3FE3FC000000000000001F03FDFE3FFFF07FC13FFFF07E01001E01FD803FFFF3FFFF", 
+        INITVAL_0D=> "0x3FFF13FFFF3FFFF3FE033C0FE0000000000000003C0FE000003FDFF007FF3FF013FFFF0020100200", 
+        INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        CSDECODE_B=> "0b001", CSDECODE_A=> "0b001", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA8=>DataInA(8), DIA7=>DataInA(7), DIA6=>DataInA(6), 
+            DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3), 
+            DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0), 
+            ADA12=>AddressA(9), ADA11=>AddressA(8), ADA10=>AddressA(7), 
+            ADA9=>AddressA(6), ADA8=>AddressA(5), ADA7=>AddressA(4), 
+            ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1), 
+            ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo, 
+            ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, 
+            WEA=>WrA, CSA2=>AddressA(12), CSA1=>AddressA(11), 
+            CSA0=>AddressA(10), RSTA=>ResetA, DIB8=>DataInB(8), 
+            DIB7=>DataInB(7), DIB6=>DataInB(6), DIB5=>DataInB(5), 
+            DIB4=>DataInB(4), DIB3=>DataInB(3), DIB2=>DataInB(2), 
+            DIB1=>DataInB(1), DIB0=>DataInB(0), ADB12=>AddressB(9), 
+            ADB11=>AddressB(8), ADB10=>AddressB(7), ADB9=>AddressB(6), 
+            ADB8=>AddressB(5), ADB7=>AddressB(4), ADB6=>AddressB(3), 
+            ADB5=>AddressB(2), ADB4=>AddressB(1), ADB3=>AddressB(0), 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vhi, 
+            CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, 
+            CSB2=>AddressB(12), CSB1=>AddressB(11), CSB0=>AddressB(10), 
+            RSTB=>ResetB, DOA8=>mdout0_1_8, DOA7=>mdout0_1_7, 
+            DOA6=>mdout0_1_6, DOA5=>mdout0_1_5, DOA4=>mdout0_1_4, 
+            DOA3=>mdout0_1_3, DOA2=>mdout0_1_2, DOA1=>mdout0_1_1, 
+            DOA0=>mdout0_1_0, DOB8=>mdout1_1_8, DOB7=>mdout1_1_7, 
+            DOB6=>mdout1_1_6, DOB5=>mdout1_1_5, DOB4=>mdout1_1_4, 
+            DOB3=>mdout1_1_3, DOB2=>mdout1_1_2, DOB1=>mdout1_1_1, 
+            DOB0=>mdout1_1_0);
+
+    gram0_2_0_4: DP8KC
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        INITVAL_1F=> "0x00000000003F83E000003FFFF3FFFF01E0100201001F01FC003E1FE3FD823FFFF387FF1FE0100201", 
+        INITVAL_1E=> "0x000000000000000001C007E0100201001E03FD801FE01002013FE0100201001C03FC02001FE3FDFE", 
+        INITVAL_1D=> "0x3FEFF0020100000301FE003813FFFE307FF3FE1F3FDFF01E0100000000000000000000381FE00400", 
+        INITVAL_1C=> "0x00000001FE303FF01E01201FE03C0000000001FE006013C3FF3FFFF3FE0700000000003FC0E003F9", 
+        INITVAL_1B=> "0x3FE3F3FBFF03FFD3FEFF000000000000000381FE3FFFF3FE3F00000000003FC1E3F07E000003E1FE", 
+        INITVAL_1A=> "0x00000000003FC3E000003FDFF3FFFF0060100201001F80FC003F1FE3FDC23FFFF383FF1FE0100201", 
+        INITVAL_19=> "0x00000000003FFFF3FFFF07E0100201001E03FD800FE01003011FE0100201001E03FC00001FC0FC00", 
+        INITVAL_18=> "0x3FC1E0020100000301FE003813FDFE383FF3FE1F3FDFF00E010000000000001FE3FDFE3FFFF00201", 
+        INITVAL_17=> "0x00000201FE383FF00E01201FE01C0000000001FE00201383FF003F91FC0000000000003FC07003F1", 
+        INITVAL_16=> "0x3FE0F3F3FF01E01002010000000000000003E1FE3FFFF3FE1F00000000003FC1E3F87F000003F0FE", 
+        INITVAL_15=> "0x00000000003FC1E000013FC06383FF0020100200001FC07C00000000000000000000000000000000", 
+        INITVAL_14=> "0x00000001003FFFF3FFFF03E0100201001F01FDC007E01003811FE0100201001F03FC00001F81FC00", 
+        INITVAL_13=> "0x3FE070020100000381FE0020000000000000000000000000000000000000201FE3FDFE3FEFF00201", 
+        INITVAL_12=> "0x00000201FE383FF00600301FE00C0000000201FE00201303FE203FF07E0000000000003FC0300201", 
+        INITVAL_11=> "0x000000000000000000000000000000000003E1FE3FFFF3FE0F00000000003FC0E3FE3F000003F07E", 
+        INITVAL_10=> "0x00000000003FC0E000013FC0E3E3FF0000000000001FE07C00000000000000000000000000000000", 
+        INITVAL_0F=> "0x00000001003FFFF3FFFF01E0100201001F80FDE007E01003C10FE0100201001F81FC00001F01FD80", 
+        INITVAL_0E=> "0x1FE0100201000003C1FE001C03FDFE3C3FF3FC023FEFF002010000000000201FE3FDFE3FEFF00201", 
+        INITVAL_0D=> "0x00000381FE3C3FF00000381FE0040000000301FE00201203FE383FF01E0100000000003FE01003FF", 
+        INITVAL_0C=> "0x3FF073FFFF20FFF3FE1F00000000000000000000001803FC0600000000003FD073FE1F000003F83E", 
+        INITVAL_0B=> "0x00000000003FC06002013FC1E3FC7F0000000000201FE03C003FDFE0FDF03FE7F3F3FF03E0100201", 
+        INITVAL_0A=> "0x000000000000000001F800E0100201001FE07DF003E01003C107E0100201001F80FC00001F03FDF0", 
+        INITVAL_09=> "0x07E0100201000003E1FE001F03FDFE3E3FF3FD823FFFF00201000000000000000000003F87E00000", 
+        INITVAL_08=> "0x000003E1FE3E3FE000003C1FE0040000000381FE00201001FE3E3FF0020100000001001FE01203FF", 
+        INITVAL_07=> "0x3FF873FFFF307FF3FE1F00000000000000000000001C03FC0600000001003FF013FE0F000003FC1E", 
+        INITVAL_06=> "0x00000000003FC03002013FD9E3FC0E0000000000201FE01C003FDFE0FDF93FE3F3F3FF03E0100201", 
+        INITVAL_05=> "0x000000000000000001FC0060100201301FE03DF801E01003E103E0100201001FC07C00001E03FDFE", 
+        INITVAL_04=> "0x01E0100201000003F0FE001F03FDFE3F3FE3FDC23FFFF00201000000000000000000003F83E00000", 
+        INITVAL_03=> "0x000003F8FE3F0FE000003E1FE0000000000381FE00200001FE3FE7F0020100000001801FE01303FF", 
+        INITVAL_02=> "0x3FF833FFFF383FF3FE0F00000000000000000000001E03FC0200000001F00FF813FE0F001003FC1E", 
+        INITVAL_01=> "0x00000000003FE03002013F9FE3FC020000000000301FE00C003FDFE07FFD3FE1F3FBFF01E0100201", 
+        INITVAL_00=> "0x000000000000000001FE00601002013F9FE005F800E01003F101E0100201001FE03C00001C03FDFE", 
+        CSDECODE_B=> "0b010", CSDECODE_A=> "0b010", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA8=>DataInA(8), DIA7=>DataInA(7), DIA6=>DataInA(6), 
+            DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3), 
+            DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0), 
+            ADA12=>AddressA(9), ADA11=>AddressA(8), ADA10=>AddressA(7), 
+            ADA9=>AddressA(6), ADA8=>AddressA(5), ADA7=>AddressA(4), 
+            ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1), 
+            ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo, 
+            ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, 
+            WEA=>WrA, CSA2=>AddressA(12), CSA1=>AddressA(11), 
+            CSA0=>AddressA(10), RSTA=>ResetA, DIB8=>DataInB(8), 
+            DIB7=>DataInB(7), DIB6=>DataInB(6), DIB5=>DataInB(5), 
+            DIB4=>DataInB(4), DIB3=>DataInB(3), DIB2=>DataInB(2), 
+            DIB1=>DataInB(1), DIB0=>DataInB(0), ADB12=>AddressB(9), 
+            ADB11=>AddressB(8), ADB10=>AddressB(7), ADB9=>AddressB(6), 
+            ADB8=>AddressB(5), ADB7=>AddressB(4), ADB6=>AddressB(3), 
+            ADB5=>AddressB(2), ADB4=>AddressB(1), ADB3=>AddressB(0), 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vhi, 
+            CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, 
+            CSB2=>AddressB(12), CSB1=>AddressB(11), CSB0=>AddressB(10), 
+            RSTB=>ResetB, DOA8=>mdout0_2_8, DOA7=>mdout0_2_7, 
+            DOA6=>mdout0_2_6, DOA5=>mdout0_2_5, DOA4=>mdout0_2_4, 
+            DOA3=>mdout0_2_3, DOA2=>mdout0_2_2, DOA1=>mdout0_2_1, 
+            DOA0=>mdout0_2_0, DOB8=>mdout1_2_8, DOB7=>mdout1_2_7, 
+            DOB6=>mdout1_2_6, DOB5=>mdout1_2_5, DOB4=>mdout1_2_4, 
+            DOB3=>mdout1_2_3, DOB2=>mdout1_2_2, DOB1=>mdout1_2_1, 
+            DOB0=>mdout1_2_0);
+
+    gram0_3_0_3: DP8KC
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1C=> "0x00000000003FDFE3FDFF3FE013FBFF0FE01002013FC06000003F80E00000000003F01E381FE00000", 
+        INITVAL_1B=> "0x000003FD063FFFF3FFFF00E0100201000000000000000000000000000000001F83FDFE3FFFF07FE1", 
+        INITVAL_1A=> "0x3FFFF1FE01001F01FC00001E03FC0000000001C007E013FE3F00000001F021FFF3FFFF3FEFF00201", 
+        INITVAL_19=> "0x00000000000000000000000000000000000381FE3FFFF3FFFF3C3FE3FDFE00E01203FF00201003FE", 
+        INITVAL_18=> "0x0020100201381FE005E007E01002013F0FE3F1FE3FFFF3FE0F201FE3FC1E3FDFE01FF93FE0700201", 
+        INITVAL_17=> "0x00000000003FDFF3FFFF3FE033FFFF3FFFF002013FC0E002013FC1E00000000003F83E3C1FE00400", 
+        INITVAL_16=> "0x001C03FD8E3FFFF3FFFF01E013F3FF07FFD3FFFF3F9FE1FC000000000000001FC3FDFE3FFFF07FF1", 
+        INITVAL_15=> "0x3FFFF3FE7F001F81FC00001F03FC0000000001E007E013FA3F00000001FE30FFF3FFFF3FE7F00381", 
+        INITVAL_14=> "0x3FFFF387FF3FFC13FFFF002010020000000381FE3FFFF3FFFF3E3FE3FDFE1FE01303FF00201201FE", 
+        INITVAL_13=> "0x00201002003C1FE005C00FE01002013FC3E3F9FF3FFFF3FE07301FE3FC1E3FDFF03FFF3FE0700201", 
+        INITVAL_12=> "0x00000000003FFFF3FFFF3FF013FFFF3FFFF03E013FC07002013FC0E00001000003FC1E381FE00C00", 
+        INITVAL_11=> "0x001F03FDC03FFFF3FFFF00E013FBFF03FFD3FEFF3FDFE0FC000000000000001FE3FDFE3FFFF03FF1", 
+        INITVAL_10=> "0x3FFFF3FFFF003FC0FC00001F01FC0000000001E003E013FA7F00000301FE383FF3FFFF3FE7F003C1", 
+        INITVAL_0F=> "0x3FFFF3C3FF1FFE13FFFF0020100000000003C1FE3FFFF3FFFF3E1FE3FDFE3FE07383FF00201301FE", 
+        INITVAL_0E=> "0x00201002003E1FE001800FE01002013FC0F3FBFF3FFFF3FE03381FE3FC1E3FFFF01FFF3FE0700201", 
+        INITVAL_0D=> "0x00000000003FDFE3FFFF3FE013FFFF3FFFF0FE013FC03002013FC0600201001003FC0E301FE01C00", 
+        INITVAL_0C=> "0x001FE0FD003FFFF3FFFF006013FBFF01FFF3FEFF3FDFE07C0100000000000000000000201FE01C00", 
+        INITVAL_0B=> "0x000003F1FE003FF07E00001F80FC0000000001F001E013F2FF000003E1FE00200000003FC3E001E0", 
+        INITVAL_0A=> "0x3FEFF3C3FF0FFF13FFFF00200000000000000000000003E0FE00000000003FE0F3C3FF00200381FE", 
+        INITVAL_09=> "0x00201000003E0FE001801FE01003013FE0100201001E03FC023C1FE3FD0E3FFFF20FFF3FE0300201", 
+        INITVAL_08=> "0x000000000000000001801FE0100201001F81FC003FE03002013FC0700201001803FC0E201FE3FDFE", 
+        INITVAL_07=> "0x3FFFF03E0100000001FE002013FFFF21FFF3FE7F3FDFE07C0100000000000000000000301FE01C00", 
+        INITVAL_06=> "0x00000201FE003FF03E01001FC07C0000000001F800E013E3FF3FFFF3FEFF00000000003FC1E001E0", 
+        INITVAL_05=> "0x3FE7F3E3FF0FFF93FFFF00000000000000000000000003F07E00000000003FC1E3E1FF00000381FE", 
+        INITVAL_04=> "0x00200000003F07E001003FFFF3FFFF0FE0100201001F03FC003E1FE3FD063FFFF307FF3FE0100201", 
+        INITVAL_03=> "0x000000000000000001800FE0100201001E03FD003FE01002013FE0300201001C03FC06201FE3FDFE", 
+        INITVAL_02=> "0x3FFFF0060100000201FE003013FFFF30FFF3FE3F3FDFE03E0100000000000000000000381FE00C00", 
+        INITVAL_01=> "0x00000001FE203FF01E01001FE07C0000000001FC00E013C3FF3FFFF3FE1F00000000003FC0E001F1", 
+        INITVAL_00=> "0x3FE7F3F3FF07FF93FFFF00000000000000000000000003F87E00000000003FC1E3E0FE000003C1FE", 
+        CSDECODE_B=> "0b011", CSDECODE_A=> "0b011", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA8=>DataInA(8), DIA7=>DataInA(7), DIA6=>DataInA(6), 
+            DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3), 
+            DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0), 
+            ADA12=>AddressA(9), ADA11=>AddressA(8), ADA10=>AddressA(7), 
+            ADA9=>AddressA(6), ADA8=>AddressA(5), ADA7=>AddressA(4), 
+            ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1), 
+            ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo, 
+            ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, 
+            WEA=>WrA, CSA2=>AddressA(12), CSA1=>AddressA(11), 
+            CSA0=>AddressA(10), RSTA=>ResetA, DIB8=>DataInB(8), 
+            DIB7=>DataInB(7), DIB6=>DataInB(6), DIB5=>DataInB(5), 
+            DIB4=>DataInB(4), DIB3=>DataInB(3), DIB2=>DataInB(2), 
+            DIB1=>DataInB(1), DIB0=>DataInB(0), ADB12=>AddressB(9), 
+            ADB11=>AddressB(8), ADB10=>AddressB(7), ADB9=>AddressB(6), 
+            ADB8=>AddressB(5), ADB7=>AddressB(4), ADB6=>AddressB(3), 
+            ADB5=>AddressB(2), ADB4=>AddressB(1), ADB3=>AddressB(0), 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vhi, 
+            CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, 
+            CSB2=>AddressB(12), CSB1=>AddressB(11), CSB0=>AddressB(10), 
+            RSTB=>ResetB, DOA8=>mdout0_3_8, DOA7=>mdout0_3_7, 
+            DOA6=>mdout0_3_6, DOA5=>mdout0_3_5, DOA4=>mdout0_3_4, 
+            DOA3=>mdout0_3_3, DOA2=>mdout0_3_2, DOA1=>mdout0_3_1, 
+            DOA0=>mdout0_3_0, DOB8=>mdout1_3_8, DOB7=>mdout1_3_7, 
+            DOB6=>mdout1_3_6, DOB5=>mdout1_3_5, DOB4=>mdout1_3_4, 
+            DOB3=>mdout1_3_3, DOB2=>mdout1_3_2, DOB1=>mdout1_3_1, 
+            DOB0=>mdout1_3_0);
+
+    gram0_4_0_2: DP8KC
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        INITVAL_1F=> "0x00000000003C40101E013FE0F003E1001F03FC003F8FE001C01FE013E303003F13FE0E3E0FE001E0", 
+        INITVAL_1E=> "0x0011E03C0E3E1FE005E01FE01003FF3FE0F3FFFF20FFF3FE3F00000000000001C078F02000E1E000", 
+        INITVAL_1D=> "0x1C00000000003C10061F3C10001D002060F3020F01C002001F3C0001C1F801E000001D1E00000000", 
+        INITVAL_1C=> "0x3FDFE0FDF03FE7F3E3FF07E010020100000001801E2010F0000020101E010003C0001E03D0001CF0", 
+        INITVAL_1B=> "0x2007E0E00000CE00020103C0001C003FAF3002000390001C00001E03FDFE3E3FF3FD823FFFF00201", 
+        INITVAL_1A=> "0x0000000000301FE00D800021E000F0000003800201DE0000701E0003E10E0023D0000E001E0000E0", 
+        INITVAL_19=> "0x201CE27006001E0000F000000001FE3FF073FFFF307FF3FE1F0000000000000003FC7E380023C000", 
+        INITVAL_18=> "0x1E00000000004F10020F0F10000D8031E073800101C000001E1E0001E18E00F003FC1F3E0FE00000", 
+        INITVAL_17=> "0x3FDFE0FDF13FE3F3F3FF03E010020100000001F00FE0103A010030100E000001C2000E01D8000478", 
+        INITVAL_16=> "0x301E607000000F10020103D0001D0031E7F003F901E013FE3F001F03FDFE3F3FE3FD823FFFF00201", 
+        INITVAL_15=> "0x00000000000F180005C02000E00070000003C00000CF0000390F0000719C0021E2000E000E000070", 
+        INITVAL_14=> "0x2007E3F0023F0FE0018007E01203FF3FF833FFFF383FF3FE0F00000000000018000438380001E000", 
+        INITVAL_13=> "0x0F00000000002712020F07180005803FA023C00000C002000F0E0003F102006012020F0018000400", 
+        INITVAL_12=> "0x3FDFE07DF93FE1F3FBFF01E0100201000000003C07800039800038100C002000E3000600D8000439", 
+        INITVAL_11=> "0x3818207C00002790020100D8000F812023F0020101C0000039001F83FDFE3F3FE3FDC03FEFF00201", 
+        INITVAL_10=> "0x0000000000079C0005C03820200038000000F80000C700027907800039F80003C3C0020003C00078", 
+        INITVAL_0F=> "0x3001E3E002000700000007800301FE3FFC13FFFF383FF3FE0F0000000000001803FC1E301FE03C00", 
+        INITVAL_0E=> "0x3FE0F3C3FF00238300063F1FE005C03E000381FE003E13FE01070001F100003E13FE073F1FE00000", 
+        INITVAL_0D=> "0x3FDFE03FFD3FE0F3FFFF00E010020100000001F003E013E2FF201FE1FC001FE013020300C003FE1F", 
+        INITVAL_0C=> "0x3810003C003FC06203FF003C1007C02021F001FE00F813FE0F001F83FDFE3F9FE1FDE03FE7F00201", 
+        INITVAL_0B=> "0x0000000000300FE0000001C013C3FF003FD00000000300030103E0101AC1001C001C001FC0000018", 
+        INITVAL_0A=> "0x300021C0003FC3E001F800201383FE3FFC13FFFF3C3FF3FE06000000000000000000000000000000", 
+        INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_08=> "0x3FDFF01FFF3FE0F3FFFF00E010020100000000000000000000000000000000000000000000000000", 
+        INITVAL_07=> "0x00000000000000000000000000000000000000000000000000001FC3FCFE3FDFE0FDF03FE3F00201", 
+        INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_05=> "0x0000000000000000000000000381FE1FFE13FFFF3E3FF3FC02000000000000000000000000000000", 
+        INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_03=> "0x3FDFF01FFF3FF073FFFF006010020100000000000000000000000000000000000000000000000000", 
+        INITVAL_02=> "0x00000000000000000000000000000000000000000000000000001FC3FC7E3FDFE07DF03FE3F00201", 
+        INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        CSDECODE_B=> "0b100", CSDECODE_A=> "0b100", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA8=>DataInA(8), DIA7=>DataInA(7), DIA6=>DataInA(6), 
+            DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3), 
+            DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0), 
+            ADA12=>AddressA(9), ADA11=>AddressA(8), ADA10=>AddressA(7), 
+            ADA9=>AddressA(6), ADA8=>AddressA(5), ADA7=>AddressA(4), 
+            ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1), 
+            ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo, 
+            ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, 
+            WEA=>WrA, CSA2=>AddressA(12), CSA1=>AddressA(11), 
+            CSA0=>AddressA(10), RSTA=>ResetA, DIB8=>DataInB(8), 
+            DIB7=>DataInB(7), DIB6=>DataInB(6), DIB5=>DataInB(5), 
+            DIB4=>DataInB(4), DIB3=>DataInB(3), DIB2=>DataInB(2), 
+            DIB1=>DataInB(1), DIB0=>DataInB(0), ADB12=>AddressB(9), 
+            ADB11=>AddressB(8), ADB10=>AddressB(7), ADB9=>AddressB(6), 
+            ADB8=>AddressB(5), ADB7=>AddressB(4), ADB6=>AddressB(3), 
+            ADB5=>AddressB(2), ADB4=>AddressB(1), ADB3=>AddressB(0), 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vhi, 
+            CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, 
+            CSB2=>AddressB(12), CSB1=>AddressB(11), CSB0=>AddressB(10), 
+            RSTB=>ResetB, DOA8=>mdout0_4_8, DOA7=>mdout0_4_7, 
+            DOA6=>mdout0_4_6, DOA5=>mdout0_4_5, DOA4=>mdout0_4_4, 
+            DOA3=>mdout0_4_3, DOA2=>mdout0_4_2, DOA1=>mdout0_4_1, 
+            DOA0=>mdout0_4_0, DOB8=>mdout1_4_8, DOB7=>mdout1_4_7, 
+            DOB6=>mdout1_4_6, DOB5=>mdout1_4_5, DOB4=>mdout1_4_4, 
+            DOB3=>mdout1_4_3, DOB2=>mdout1_4_2, DOB1=>mdout1_4_1, 
+            DOB0=>mdout1_4_0);
+
+    gram0_5_0_1: DP8KC
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_03=> "0x0000000000000000000000000000000000000000000000000000000000000000001CE0001E003C00", 
+        INITVAL_02=> "0x38000001FE000003F802001FC01C000020F003E0003011FE0038000381C001D003FC3E001FE01C00", 
+        INITVAL_01=> "0x3F1FE0FDC03FE3F3C3FF03E010020100000381E01C000381FE0020103C003FC0E001F101E013F3FF", 
+        INITVAL_00=> "0x0001E1C0003F87E001F800E0103A013C2E1003F907E013FAFF001C03FDFE3C3FF3FF063FFFF00601", 
+        CSDECODE_B=> "0b101", CSDECODE_A=> "0b101", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA8=>DataInA(8), DIA7=>DataInA(7), DIA6=>DataInA(6), 
+            DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3), 
+            DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0), 
+            ADA12=>AddressA(9), ADA11=>AddressA(8), ADA10=>AddressA(7), 
+            ADA9=>AddressA(6), ADA8=>AddressA(5), ADA7=>AddressA(4), 
+            ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1), 
+            ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo, 
+            ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, 
+            WEA=>WrA, CSA2=>AddressA(12), CSA1=>AddressA(11), 
+            CSA0=>AddressA(10), RSTA=>ResetA, DIB8=>DataInB(8), 
+            DIB7=>DataInB(7), DIB6=>DataInB(6), DIB5=>DataInB(5), 
+            DIB4=>DataInB(4), DIB3=>DataInB(3), DIB2=>DataInB(2), 
+            DIB1=>DataInB(1), DIB0=>DataInB(0), ADB12=>AddressB(9), 
+            ADB11=>AddressB(8), ADB10=>AddressB(7), ADB9=>AddressB(6), 
+            ADB8=>AddressB(5), ADB7=>AddressB(4), ADB6=>AddressB(3), 
+            ADB5=>AddressB(2), ADB4=>AddressB(1), ADB3=>AddressB(0), 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vhi, 
+            CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, 
+            CSB2=>AddressB(12), CSB1=>AddressB(11), CSB0=>AddressB(10), 
+            RSTB=>ResetB, DOA8=>mdout0_5_8, DOA7=>mdout0_5_7, 
+            DOA6=>mdout0_5_6, DOA5=>mdout0_5_5, DOA4=>mdout0_5_4, 
+            DOA3=>mdout0_5_3, DOA2=>mdout0_5_2, DOA1=>mdout0_5_1, 
+            DOA0=>mdout0_5_0, DOB8=>mdout1_5_8, DOB7=>mdout1_5_7, 
+            DOB6=>mdout1_5_6, DOB5=>mdout1_5_5, DOB4=>mdout1_5_4, 
+            DOB3=>mdout1_5_3, DOB2=>mdout1_5_2, DOB1=>mdout1_5_1, 
+            DOB0=>mdout1_5_0);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    gram0_6_0_0: DP8KC
+        generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC", 
+        INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", 
+        CSDECODE_B=> "0b110", CSDECODE_A=> "0b110", WRITEMODE_B=> "NORMAL", 
+        WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", 
+        REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=>  9, 
+        DATA_WIDTH_A=>  9)
+        port map (DIA8=>DataInA(8), DIA7=>DataInA(7), DIA6=>DataInA(6), 
+            DIA5=>DataInA(5), DIA4=>DataInA(4), DIA3=>DataInA(3), 
+            DIA2=>DataInA(2), DIA1=>DataInA(1), DIA0=>DataInA(0), 
+            ADA12=>AddressA(9), ADA11=>AddressA(8), ADA10=>AddressA(7), 
+            ADA9=>AddressA(6), ADA8=>AddressA(5), ADA7=>AddressA(4), 
+            ADA6=>AddressA(3), ADA5=>AddressA(2), ADA4=>AddressA(1), 
+            ADA3=>AddressA(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo, 
+            ADA0=>scuba_vhi, CEA=>ClockEnA, OCEA=>ClockEnA, CLKA=>ClockA, 
+            WEA=>WrA, CSA2=>AddressA(12), CSA1=>AddressA(11), 
+            CSA0=>AddressA(10), RSTA=>ResetA, DIB8=>DataInB(8), 
+            DIB7=>DataInB(7), DIB6=>DataInB(6), DIB5=>DataInB(5), 
+            DIB4=>DataInB(4), DIB3=>DataInB(3), DIB2=>DataInB(2), 
+            DIB1=>DataInB(1), DIB0=>DataInB(0), ADB12=>AddressB(9), 
+            ADB11=>AddressB(8), ADB10=>AddressB(7), ADB9=>AddressB(6), 
+            ADB8=>AddressB(5), ADB7=>AddressB(4), ADB6=>AddressB(3), 
+            ADB5=>AddressB(2), ADB4=>AddressB(1), ADB3=>AddressB(0), 
+            ADB2=>scuba_vlo, ADB1=>scuba_vlo, ADB0=>scuba_vhi, 
+            CEB=>ClockEnB, OCEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, 
+            CSB2=>AddressB(12), CSB1=>AddressB(11), CSB0=>AddressB(10), 
+            RSTB=>ResetB, DOA8=>mdout0_6_8, DOA7=>mdout0_6_7, 
+            DOA6=>mdout0_6_6, DOA5=>mdout0_6_5, DOA4=>mdout0_6_4, 
+            DOA3=>mdout0_6_3, DOA2=>mdout0_6_2, DOA1=>mdout0_6_1, 
+            DOA0=>mdout0_6_0, DOB8=>mdout1_6_8, DOB7=>mdout1_6_7, 
+            DOB6=>mdout1_6_6, DOB5=>mdout1_6_5, DOB4=>mdout1_6_4, 
+            DOB3=>mdout1_6_3, DOB2=>mdout1_6_2, DOB1=>mdout1_6_1, 
+            DOB0=>mdout1_6_0);
+
+    FF_11: FD1P3DX
+        port map (D=>AddressA(10), SP=>wren0_inv_g, CK=>ClockA, 
+            CD=>scuba_vlo, Q=>addr010_ff);
+
+    FF_10: FD1P3DX
+        port map (D=>AddressA(11), SP=>wren0_inv_g, CK=>ClockA, 
+            CD=>scuba_vlo, Q=>addr011_ff);
+
+    FF_9: FD1P3DX
+        port map (D=>AddressA(12), SP=>wren0_inv_g, CK=>ClockA, 
+            CD=>scuba_vlo, Q=>addr012_ff);
+
+    FF_8: FD1P3DX
+        port map (D=>addr010_ff, SP=>ClockEnA, CK=>ClockA, CD=>scuba_vlo, 
+            Q=>addr010_ff2);
+
+    FF_7: FD1P3DX
+        port map (D=>addr011_ff, SP=>ClockEnA, CK=>ClockA, CD=>scuba_vlo, 
+            Q=>addr011_ff2);
+
+    FF_6: FD1P3DX
+        port map (D=>addr012_ff, SP=>ClockEnA, CK=>ClockA, CD=>scuba_vlo, 
+            Q=>addr012_ff2);
+
+    FF_5: FD1P3DX
+        port map (D=>AddressB(10), SP=>wren1_inv_g, CK=>ClockB, 
+            CD=>scuba_vlo, Q=>addr110_ff);
+
+    FF_4: FD1P3DX
+        port map (D=>AddressB(11), SP=>wren1_inv_g, CK=>ClockB, 
+            CD=>scuba_vlo, Q=>addr111_ff);
+
+    FF_3: FD1P3DX
+        port map (D=>AddressB(12), SP=>wren1_inv_g, CK=>ClockB, 
+            CD=>scuba_vlo, Q=>addr112_ff);
+
+    FF_2: FD1P3DX
+        port map (D=>addr110_ff, SP=>ClockEnB, CK=>ClockB, CD=>scuba_vlo, 
+            Q=>addr110_ff2);
+
+    FF_1: FD1P3DX
+        port map (D=>addr111_ff, SP=>ClockEnB, CK=>ClockB, CD=>scuba_vlo, 
+            Q=>addr111_ff2);
+
+    FF_0: FD1P3DX
+        port map (D=>addr112_ff, SP=>ClockEnB, CK=>ClockB, CD=>scuba_vlo, 
+            Q=>addr112_ff2);
+
+    mux_17: MUX81
+        port map (D0=>mdout0_0_0, D1=>mdout0_1_0, D2=>mdout0_2_0, 
+            D3=>mdout0_3_0, D4=>mdout0_4_0, D5=>mdout0_5_0, 
+            D6=>mdout0_6_0, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(0));
+
+    mux_16: MUX81
+        port map (D0=>mdout0_0_1, D1=>mdout0_1_1, D2=>mdout0_2_1, 
+            D3=>mdout0_3_1, D4=>mdout0_4_1, D5=>mdout0_5_1, 
+            D6=>mdout0_6_1, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(1));
+
+    mux_15: MUX81
+        port map (D0=>mdout0_0_2, D1=>mdout0_1_2, D2=>mdout0_2_2, 
+            D3=>mdout0_3_2, D4=>mdout0_4_2, D5=>mdout0_5_2, 
+            D6=>mdout0_6_2, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(2));
+
+    mux_14: MUX81
+        port map (D0=>mdout0_0_3, D1=>mdout0_1_3, D2=>mdout0_2_3, 
+            D3=>mdout0_3_3, D4=>mdout0_4_3, D5=>mdout0_5_3, 
+            D6=>mdout0_6_3, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(3));
+
+    mux_13: MUX81
+        port map (D0=>mdout0_0_4, D1=>mdout0_1_4, D2=>mdout0_2_4, 
+            D3=>mdout0_3_4, D4=>mdout0_4_4, D5=>mdout0_5_4, 
+            D6=>mdout0_6_4, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(4));
+
+    mux_12: MUX81
+        port map (D0=>mdout0_0_5, D1=>mdout0_1_5, D2=>mdout0_2_5, 
+            D3=>mdout0_3_5, D4=>mdout0_4_5, D5=>mdout0_5_5, 
+            D6=>mdout0_6_5, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(5));
+
+    mux_11: MUX81
+        port map (D0=>mdout0_0_6, D1=>mdout0_1_6, D2=>mdout0_2_6, 
+            D3=>mdout0_3_6, D4=>mdout0_4_6, D5=>mdout0_5_6, 
+            D6=>mdout0_6_6, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(6));
+
+    mux_10: MUX81
+        port map (D0=>mdout0_0_7, D1=>mdout0_1_7, D2=>mdout0_2_7, 
+            D3=>mdout0_3_7, D4=>mdout0_4_7, D5=>mdout0_5_7, 
+            D6=>mdout0_6_7, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(7));
+
+    mux_9: MUX81
+        port map (D0=>mdout0_0_8, D1=>mdout0_1_8, D2=>mdout0_2_8, 
+            D3=>mdout0_3_8, D4=>mdout0_4_8, D5=>mdout0_5_8, 
+            D6=>mdout0_6_8, D7=>scuba_vlo, SD1=>addr010_ff2, 
+            SD2=>addr011_ff2, SD3=>addr012_ff2, Z=>QA(8));
+
+    mux_8: MUX81
+        port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0, 
+            D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0, 
+            D6=>mdout1_6_0, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(0));
+
+    mux_7: MUX81
+        port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1, 
+            D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1, 
+            D6=>mdout1_6_1, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(1));
+
+    mux_6: MUX81
+        port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2, 
+            D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2, 
+            D6=>mdout1_6_2, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(2));
+
+    mux_5: MUX81
+        port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3, 
+            D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3, 
+            D6=>mdout1_6_3, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(3));
+
+    mux_4: MUX81
+        port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4, 
+            D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4, 
+            D6=>mdout1_6_4, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(4));
+
+    mux_3: MUX81
+        port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5, 
+            D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5, 
+            D6=>mdout1_6_5, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(5));
+
+    mux_2: MUX81
+        port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6, 
+            D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6, 
+            D6=>mdout1_6_6, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(6));
+
+    mux_1: MUX81
+        port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7, 
+            D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7, 
+            D6=>mdout1_6_7, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(7));
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    mux_0: MUX81
+        port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8, 
+            D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8, 
+            D6=>mdout1_6_8, D7=>scuba_vlo, SD1=>addr110_ff2, 
+            SD2=>addr111_ff2, SD3=>addr112_ff2, Z=>QB(8));
+
+end Structure;
+
+-- synopsys translate_off
+library MACHXO2;
+configuration Structure_CON of gram0 is
+    for Structure
+        for all:AND2 use entity MACHXO2.AND2(V); end for;
+        for all:FD1P3DX use entity MACHXO2.FD1P3DX(V); end for;
+        for all:INV use entity MACHXO2.INV(V); end for;
+        for all:MUX81 use entity MACHXO2.MUX81(V); end for;
+        for all:VHI use entity MACHXO2.VHI(V); end for;
+        for all:VLO use entity MACHXO2.VLO(V); end for;
+        for all:DP8KC use entity MACHXO2.DP8KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- a/display/fpga/ip/gram0/gram0_generate.log
+++ b/display/fpga/ip/gram0/gram0_generate.log
@ -0,0 +1,49 @@
+Starting process: Module
+
+Starting process: 
+
+SCUBA, Version Diamond (64-bit) 3.10.0.111.2
+Sun Apr 22 17:34:06 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-1200HC -aaddr_width 13 -widtha 9 -baddr_width 13 -widthb 9 -anum_words 7000 -bnum_words 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL 
+    Circuit name     : gram0
+    Module type      : RAM_DP_TRUE
+    Module Version   : 7.5
+    Ports            : 
+	Inputs       : DataInA[8:0], DataInB[8:0], AddressA[12:0], AddressB[12:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
+	Outputs      : QA[8:0], QB[8:0]
+    I/O buffer       : not inserted
+    Memory file      : /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem
+    EDIF output      : gram0.edn
+    VHDL output      : gram0.vhd
+    VHDL template    : gram0_tmpl.vhd
+    VHDL testbench   : tb_gram0_tmpl.vhd
+    VHDL purpose     : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : gram0.srp
+    Estimated Resource Usage:
+            LUT : 38
+            EBR : 7
+            Reg : 12
+
+END   SCUBA Module Synthesis
+
+File: gram0.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
--- a/display/fpga/ip/gram0/gram0_tmpl.vhd
+++ b/display/fpga/ip/gram0/gram0_tmpl.vhd
@ -0,0 +1,23 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
+-- Module  Version: 7.5
+-- Sun Apr 22 17:34:06 2018
+
+-- parameterized module component declaration
+component gram0
+    port (DataInA: in  std_logic_vector(8 downto 0); 
+        DataInB: in  std_logic_vector(8 downto 0); 
+        AddressA: in  std_logic_vector(12 downto 0); 
+        AddressB: in  std_logic_vector(12 downto 0); 
+        ClockA: in  std_logic; ClockB: in  std_logic; 
+        ClockEnA: in  std_logic; ClockEnB: in  std_logic; 
+        WrA: in  std_logic; WrB: in  std_logic; ResetA: in  std_logic; 
+        ResetB: in  std_logic; QA: out  std_logic_vector(8 downto 0); 
+        QB: out  std_logic_vector(8 downto 0));
+end component;
+
+-- parameterized module component instance
+__ : gram0
+    port map (DataInA(8 downto 0)=>__, DataInB(8 downto 0)=>__, AddressA(12 downto 0)=>__, 
+        AddressB(12 downto 0)=>__, ClockA=>__, ClockB=>__, ClockEnA=>__, 
+        ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, ResetB=>__, QA(8 downto 0)=>__, 
+        QB(8 downto 0)=>__);
--- a/display/fpga/ip/gram0/msg_file.log
+++ b/display/fpga/ip/gram0/msg_file.log
@ -0,0 +1,34 @@
+SCUBA, Version Diamond (64-bit) 3.10.0.111.2
+Sun Apr 22 17:34:06 2018
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-1200HC -aaddr_width 13 -widtha 9 -baddr_width 13 -widthb 9 -anum_words 7000 -bnum_words 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL 
+    Circuit name     : gram0
+    Module type      : RAM_DP_TRUE
+    Module Version   : 7.5
+    Ports            : 
+    Inputs       : DataInA[8:0], DataInB[8:0], AddressA[12:0], AddressB[12:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
+    Outputs      : QA[8:0], QB[8:0]
+    I/O buffer       : not inserted
+    Memory file      : /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem
+    EDIF output      : gram0.edn
+    VHDL output      : gram0.vhd
+    VHDL template    : gram0_tmpl.vhd
+    VHDL testbench   : tb_gram0_tmpl.vhd
+    VHDL purpose     : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : gram0.srp
+    Estimated Resource Usage:
+            LUT : 38
+            EBR : 7
+            Reg : 12
+  
+END   SCUBA Module Synthesis
+
--- a/display/fpga/ip/gram0/tb_gram0_tmpl.vhd
+++ b/display/fpga/ip/gram0/tb_gram0_tmpl.vhd
@ -0,0 +1,178 @@
+-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.10.0.111.2
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use IEEE.math_real.all;
+
+use IEEE.numeric_std.all;
+
+entity tb is
+end entity tb;
+
+
+architecture test of tb is 
+
+    component gram0
+        port (DataInA : in std_logic_vector(8 downto 0); 
+        DataInB : in std_logic_vector(8 downto 0); 
+        AddressA : in std_logic_vector(12 downto 0); 
+        AddressB : in std_logic_vector(12 downto 0); 
+        ClockA: in std_logic; ClockB: in std_logic; 
+        ClockEnA: in std_logic; ClockEnB: in std_logic; 
+        WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic; 
+        ResetB: in std_logic; QA : out std_logic_vector(8 downto 0); 
+        QB : out std_logic_vector(8 downto 0)
+    );
+    end component;
+
+    signal DataInA : std_logic_vector(8 downto 0) := (others => '0');
+    signal DataInB : std_logic_vector(8 downto 0) := (others => '0');
+    signal AddressA : std_logic_vector(12 downto 0) := (others => '0');
+    signal AddressB : std_logic_vector(12 downto 0) := (others => '0');
+    signal ClockA: std_logic := '0';
+    signal ClockB: std_logic := '0';
+    signal ClockEnA: std_logic := '0';
+    signal ClockEnB: std_logic := '0';
+    signal WrA: std_logic := '0';
+    signal WrB: std_logic := '0';
+    signal ResetA: std_logic := '0';
+    signal ResetB: std_logic := '0';
+    signal QA : std_logic_vector(8 downto 0);
+    signal QB : std_logic_vector(8 downto 0);
+begin
+    u1 : gram0
+        port map (DataInA => DataInA, DataInB => DataInB, AddressA => AddressA, 
+            AddressB => AddressB, ClockA => ClockA, ClockB => ClockB, 
+            ClockEnA => ClockEnA, ClockEnB => ClockEnB, WrA => WrA, WrB => WrB, 
+            ResetA => ResetA, ResetB => ResetB, QA => QA, QB => QB
+        );
+
+    process
+
+    begin
+      DataInA <= (others => '0') ;
+      wait for 100 ns;
+      wait until ResetA = '0';
+      for i in 0 to 7003 loop
+        wait until ClockA'event and ClockA = '1';
+        DataInA <= DataInA + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    process
+
+    begin
+      DataInB <= (others => '0') ;
+      wait for 100 ns;
+      wait until ResetB = '0';
+      wait until WrB = '1';
+      for i in 0 to 7003 loop
+        wait until ClockB'event and ClockB = '1';
+        DataInB <= DataInB + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    process
+
+    begin
+      AddressA <= (others => '0') ;
+      wait for 100 ns;
+      wait until ResetA = '0';
+      for i in 0 to 14006 loop
+        wait until ClockA'event and ClockA = '1';
+        AddressA <= AddressA + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    process
+
+    begin
+      AddressB <= (others => '0') ;
+      wait for 100 ns;
+      wait until ResetB = '0';
+      wait until WrB = '1';
+      for i in 0 to 14006 loop
+        wait until ClockB'event and ClockB = '1';
+        AddressB <= AddressB + '1' after 1 ns;
+      end loop;
+      wait;
+    end process;
+
+    ClockA <= not ClockA after 5.00 ns;
+
+    ClockB <= not ClockB after 5.00 ns;
+
+    process
+
+    begin
+      ClockEnA <= '0' ;
+      wait for 100 ns;
+      wait until ResetA = '0';
+      ClockEnA <= '1' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      ClockEnB <= '0' ;
+      wait for 100 ns;
+      wait until ResetB = '0';
+      ClockEnB <= '1' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      WrA <= '0' ;
+      wait until ResetA = '0';
+      for i in 0 to 7003 loop
+        wait until ClockA'event and ClockA = '1';
+        WrA <= '1' after 1 ns;
+      end loop;
+      WrA <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      WrB <= '0' ;
+      wait until ResetB = '0';
+      wait until WrA = '1';
+      wait until WrA = '0';
+      for i in 0 to 7003 loop
+        wait until ClockA'event and ClockA = '1';
+      end loop;
+      for i in 0 to 7003 loop
+        wait until ClockB'event and ClockB = '1';
+        WrB <= '1' after 1 ns;
+      end loop;
+      WrB <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      ResetA <= '1' ;
+      wait for 100 ns;
+      ResetA <= '0' ;
+      wait;
+    end process;
+
+    process
+
+    begin
+      ResetB <= '1' ;
+      wait for 100 ns;
+      ResetB <= '0' ;
+      wait;
+    end process;
+
+end architecture test;
--- a/display/fpga/ip/pll0/._Real_._Math_.vhd
+++ b/display/fpga/ip/pll0/._Real_._Math_.vhd
--- a/display/fpga/ip/pll0/generate_core.tcl
+++ b/display/fpga/ip/pll0/generate_core.tcl
@ -0,0 +1,100 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+proc GetCmdLine {lpcfile} {
+	global Para
+
+	if [catch {open $lpcfile r} fileid] {
+		puts "Cannot open $para_file file!"
+		exit -1
+	}
+
+	seek $fileid 0 start
+	set default_match 0
+	while {[gets $fileid line] >= 0} {
+		if {[string first "\[Command\]" $line] == 0} {
+			set default_match 1
+			continue
+		}
+		if {[string first "\[" $line] == 0} {
+			set default_match 0
+		}
+		if {$default_match == 1} {
+			if [regexp {([^=]*)=(.*)} $line match parameter value] {
+				if [regexp {([ |\t]*;)} $parameter match] {continue}
+				if [regexp {(.*)[ |\t]*;} $value match temp] {
+					set Para($parameter) $temp
+				} else {
+					set Para($parameter) $value
+				}
+			}
+		}
+	}
+	set default_match 0
+	close $fileid
+
+	return $Para(cmd_line)
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+
+set scuba "$Para(FPGAPath)/scuba"
+set modulename "pll0"
+set lang "vhdl"
+set lpcfile "$Para(sbp_path)/$modulename.lpc"
+set arch "xo2c00"
+set cmd_line [GetCmdLine $lpcfile]
+set fdcfile "$Para(sbp_path)/$modulename.fdc"
+if {[file exists $fdcfile] == 0} {
+	append scuba " " $cmd_line
+} else {
+	append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
+}
+set Para(result) [catch {eval exec "$scuba"} msg]
+#puts $msg
--- a/display/fpga/ip/pll0/generate_ngd.tcl
+++ b/display/fpga/ip/pll0/generate_ngd.tcl
@ -0,0 +1,115 @@
+#!/usr/local/bin/wish
+
+proc GetPlatform {} {
+	global tcl_platform
+
+	set cpu  $tcl_platform(machine)
+
+	switch $cpu {
+		intel -
+		i*86* {
+			set cpu ix86
+		}
+		x86_64 {
+			if {$tcl_platform(wordSize) == 4} {
+				set cpu ix86
+			}
+		}
+	}
+
+	switch $tcl_platform(platform) {
+		windows {
+			if {$cpu == "amd64"} {
+				# Do not check wordSize, win32-x64 is an IL32P64 platform.
+				set cpu x86_64
+			}
+			if {$cpu == "x86_64"} {
+				return "nt64"
+			} else {
+				return "nt"
+			}
+		}
+		unix {
+			if {$tcl_platform(os) == "Linux"}  {
+				if {$cpu == "x86_64"} {
+					return "lin64"
+				} else {
+					return "lin"
+				}
+			} else  {
+				return "sol"
+			}
+		}
+	}
+	return "nt"
+}
+
+set platformpath [GetPlatform]
+set Para(sbp_path) [file dirname [info script]]
+set Para(install_dir) $env(TOOLRTF)
+set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
+set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
+
+set Para(ModuleName) "pll0"
+set Para(Module) "PLL"
+set Para(libname) machxo2
+set Para(arch_name) xo2c00
+set Para(PartType) "LCMXO2-1200HC"
+
+set Para(tech_syn) machxo2
+set Para(tech_cae) machxo2
+set Para(Package) "QFN32"
+set Para(SpeedGrade) "5"
+set Para(FMax) "100"
+set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
+
+#create response file(*.cmd) for Synpwrap
+proc CreateCmdFile {} {
+	global Para
+
+	file mkdir "$Para(sbp_path)/syn_results"
+	if [catch {open $Para(ModuleName).cmd w} rspFile] {
+		puts "Cannot create response file $Para(ModuleName).cmd."
+		exit -1
+	} else {
+		puts $rspFile "PROJECT: $Para(ModuleName)
+		working_path: \"$Para(sbp_path)/syn_results\"
+		module: $Para(ModuleName)
+		verilog_file_list: \"$Para(sbp_path)/$Para(ModuleName).vhd\"
+		vlog_std_v2001: true
+		constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
+		suffix_name: edn
+		output_file_name: $Para(ModuleName)
+		write_prf: true
+		disable_io_insertion: true
+		force_gsr: false
+		frequency: $Para(FMax)
+		fanout_limit: 50
+		retiming: false
+		pipe: false
+		part: $Para(PartType)
+		speed_grade: $Para(SpeedGrade)
+		"
+		close $rspFile
+	}
+}
+
+#synpwrap
+CreateCmdFile
+set synpwrap "$Para(bin_dir)/synpwrap"
+if {[file exists $fdcfile] == 0} {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
+} else {
+	set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
+}
+#puts $msg
+
+#edif2ngd
+set edif2ngd "$Para(FPGAPath)/edif2ngd"
+set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
+#puts $msg
+
+#ngdbuild
+set ngdbuild "$Para(FPGAPath)/ngdbuild"
+set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
+#puts $msg
--- a/display/fpga/ip/pll0/msg_file.log
+++ b/display/fpga/ip/pll0/msg_file.log
@ -0,0 +1,29 @@
+SCUBA, Version Diamond (64-bit) 3.10.0.111.2
+Tue Apr 24 22:15:53 2018
+  
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+  
+BEGIN SCUBA Module Synthesis
+  
+    Issued command   : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock 
+    Circuit name     : pll0
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+    Inputs       : CLKI
+    Outputs      : CLKOP, LOCK
+    I/O buffer       : not inserted
+    EDIF output      : pll0.edn
+    VHDL output      : pll0.vhd
+    VHDL template    : pll0_tmpl.vhd
+    VHDL purpose     : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll0.srp
+    Estimated Resource Usage:
+  
+END   SCUBA Module Synthesis
+
--- a/display/fpga/ip/pll0/pll0.cst
+++ b/display/fpga/ip/pll0/pll0.cst
@ -0,0 +1,3 @@
+Date=04/24/2018
+Time=22:15:53
+
--- a/display/fpga/ip/pll0/pll0.edn
+++ b/display/fpga/ip/pll0/pll0.edn
@ -0,0 +1,300 @@
+(edif pll0
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2018 4 24 22 15 53)
+      (program "SCUBA" (version "Diamond (64-bit) 3.10.0.111.2"))))
+      (comment "/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell EHXPLLJ
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKFB
+            (direction INPUT))
+          (port PHASESEL1
+            (direction INPUT))
+          (port PHASESEL0
+            (direction INPUT))
+          (port PHASEDIR
+            (direction INPUT))
+          (port PHASESTEP
+            (direction INPUT))
+          (port LOADREG
+            (direction INPUT))
+          (port STDBY
+            (direction INPUT))
+          (port PLLWAKESYNC
+            (direction INPUT))
+          (port RST
+            (direction INPUT))
+          (port RESETM
+            (direction INPUT))
+          (port RESETC
+            (direction INPUT))
+          (port RESETD
+            (direction INPUT))
+          (port ENCLKOP
+            (direction INPUT))
+          (port ENCLKOS
+            (direction INPUT))
+          (port ENCLKOS2
+            (direction INPUT))
+          (port ENCLKOS3
+            (direction INPUT))
+          (port PLLCLK
+            (direction INPUT))
+          (port PLLRST
+            (direction INPUT))
+          (port PLLSTB
+            (direction INPUT))
+          (port PLLWE
+            (direction INPUT))
+          (port PLLADDR4
+            (direction INPUT))
+          (port PLLADDR3
+            (direction INPUT))
+          (port PLLADDR2
+            (direction INPUT))
+          (port PLLADDR1
+            (direction INPUT))
+          (port PLLADDR0
+            (direction INPUT))
+          (port PLLDATI7
+            (direction INPUT))
+          (port PLLDATI6
+            (direction INPUT))
+          (port PLLDATI5
+            (direction INPUT))
+          (port PLLDATI4
+            (direction INPUT))
+          (port PLLDATI3
+            (direction INPUT))
+          (port PLLDATI2
+            (direction INPUT))
+          (port PLLDATI1
+            (direction INPUT))
+          (port PLLDATI0
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port CLKOS
+            (direction OUTPUT))
+          (port CLKOS2
+            (direction OUTPUT))
+          (port CLKOS3
+            (direction OUTPUT))
+          (port LOCK
+            (direction OUTPUT))
+          (port INTLOCK
+            (direction OUTPUT))
+          (port REFCLK
+            (direction OUTPUT))
+          (port CLKINTFB
+            (direction OUTPUT))
+          (port DPHSRC
+            (direction OUTPUT))
+          (port PLLACK
+            (direction OUTPUT))
+          (port PLLDATO7
+            (direction OUTPUT))
+          (port PLLDATO6
+            (direction OUTPUT))
+          (port PLLDATO5
+            (direction OUTPUT))
+          (port PLLDATO4
+            (direction OUTPUT))
+          (port PLLDATO3
+            (direction OUTPUT))
+          (port PLLDATO2
+            (direction OUTPUT))
+          (port PLLDATO1
+            (direction OUTPUT))
+          (port PLLDATO0
+            (direction OUTPUT)))))
+    (cell pll0
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CLKI
+            (direction INPUT))
+          (port CLKOP
+            (direction OUTPUT))
+          (port LOCK
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance PLLInst_0
+            (viewRef view1 
+              (cellRef EHXPLLJ))
+            (property DDRST_ENA
+              (string "DISABLED"))
+            (property DCRST_ENA
+              (string "DISABLED"))
+            (property MRST_ENA
+              (string "DISABLED"))
+            (property PLLRST_ENA
+              (string "DISABLED"))
+            (property INTFB_WAKE
+              (string "DISABLED"))
+            (property STDBY_ENABLE
+              (string "DISABLED"))
+            (property DPHASE_SOURCE
+              (string "DISABLED"))
+            (property PLL_USE_WB
+              (string "DISABLED"))
+            (property CLKOS3_FPHASE
+              (string "0"))
+            (property CLKOS3_CPHASE
+              (string "0"))
+            (property CLKOS2_FPHASE
+              (string "0"))
+            (property CLKOS2_CPHASE
+              (string "0"))
+            (property CLKOS_FPHASE
+              (string "0"))
+            (property CLKOS_CPHASE
+              (string "0"))
+            (property CLKOP_FPHASE
+              (string "0"))
+            (property CLKOP_CPHASE
+              (string "4"))
+            (property PLL_LOCK_MODE
+              (string "0"))
+            (property CLKOS_TRIM_DELAY
+              (string "0"))
+            (property CLKOS_TRIM_POL
+              (string "FALLING"))
+            (property CLKOP_TRIM_DELAY
+              (string "0"))
+            (property CLKOP_TRIM_POL
+              (string "RISING"))
+            (property FRACN_DIV
+              (string "0"))
+            (property FRACN_ENABLE
+              (string "DISABLED"))
+            (property OUTDIVIDER_MUXD2
+              (string "DIVD"))
+            (property PREDIVIDER_MUXD1
+              (string "0"))
+            (property VCO_BYPASS_D0
+              (string "DISABLED"))
+            (property CLKOS3_ENABLE
+              (string "DISABLED"))
+            (property OUTDIVIDER_MUXC2
+              (string "DIVC"))
+            (property PREDIVIDER_MUXC1
+              (string "0"))
+            (property VCO_BYPASS_C0
+              (string "DISABLED"))
+            (property CLKOS2_ENABLE
+              (string "DISABLED"))
+            (property OUTDIVIDER_MUXB2
+              (string "DIVB"))
+            (property PREDIVIDER_MUXB1
+              (string "0"))
+            (property VCO_BYPASS_B0
+              (string "DISABLED"))
+            (property CLKOS_ENABLE
+              (string "DISABLED"))
+            (property FREQUENCY_PIN_CLKOP
+              (string "96.000000"))
+            (property OUTDIVIDER_MUXA2
+              (string "DIVA"))
+            (property PREDIVIDER_MUXA1
+              (string "0"))
+            (property VCO_BYPASS_A0
+              (string "DISABLED"))
+            (property CLKOP_ENABLE
+              (string "ENABLED"))
+            (property FREQUENCY_PIN_CLKI
+              (string "12.000000"))
+            (property ICP_CURRENT
+              (string "7"))
+            (property LPF_RESISTOR
+              (string "8"))
+            (property CLKOS3_DIV
+              (string "1"))
+            (property CLKOS2_DIV
+              (string "1"))
+            (property CLKOS_DIV
+              (string "1"))
+            (property CLKOP_DIV
+              (string "5"))
+            (property CLKFB_DIV
+              (string "8"))
+            (property CLKI_DIV
+              (string "1"))
+            (property FEEDBK_PATH
+              (string "CLKOP")))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef PLLADDR4 (instanceRef PLLInst_0))
+              (portRef PLLADDR3 (instanceRef PLLInst_0))
+              (portRef PLLADDR2 (instanceRef PLLInst_0))
+              (portRef PLLADDR1 (instanceRef PLLInst_0))
+              (portRef PLLADDR0 (instanceRef PLLInst_0))
+              (portRef PLLDATI7 (instanceRef PLLInst_0))
+              (portRef PLLDATI6 (instanceRef PLLInst_0))
+              (portRef PLLDATI5 (instanceRef PLLInst_0))
+              (portRef PLLDATI4 (instanceRef PLLInst_0))
+              (portRef PLLDATI3 (instanceRef PLLInst_0))
+              (portRef PLLDATI2 (instanceRef PLLInst_0))
+              (portRef PLLDATI1 (instanceRef PLLInst_0))
+              (portRef PLLDATI0 (instanceRef PLLInst_0))
+              (portRef PLLWE (instanceRef PLLInst_0))
+              (portRef PLLSTB (instanceRef PLLInst_0))
+              (portRef PLLRST (instanceRef PLLInst_0))
+              (portRef PLLCLK (instanceRef PLLInst_0))
+              (portRef ENCLKOS3 (instanceRef PLLInst_0))
+              (portRef ENCLKOS2 (instanceRef PLLInst_0))
+              (portRef ENCLKOS (instanceRef PLLInst_0))
+              (portRef ENCLKOP (instanceRef PLLInst_0))
+              (portRef RESETD (instanceRef PLLInst_0))
+              (portRef RESETC (instanceRef PLLInst_0))
+              (portRef RESETM (instanceRef PLLInst_0))
+              (portRef RST (instanceRef PLLInst_0))
+              (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+              (portRef STDBY (instanceRef PLLInst_0))
+              (portRef LOADREG (instanceRef PLLInst_0))
+              (portRef PHASESTEP (instanceRef PLLInst_0))
+              (portRef PHASEDIR (instanceRef PLLInst_0))
+              (portRef PHASESEL1 (instanceRef PLLInst_0))
+              (portRef PHASESEL0 (instanceRef PLLInst_0))))
+          (net LOCK
+            (joined
+              (portRef LOCK)
+              (portRef LOCK (instanceRef PLLInst_0))))
+          (net CLKOP
+            (joined
+              (portRef CLKOP)
+              (portRef CLKFB (instanceRef PLLInst_0))
+              (portRef CLKOP (instanceRef PLLInst_0))))
+          (net CLKI
+            (joined
+              (portRef CLKI)
+              (portRef CLKI (instanceRef PLLInst_0))))))))
+  (design pll0
+    (cellRef pll0
+      (libraryRef ORCLIB)))
+)
--- a/display/fpga/ip/pll0/pll0.jhd
+++ b/display/fpga/ip/pll0/pll0.jhd
@ -0,0 +1,5 @@
+MODULE pll0 DEFIN pll0.vhd
+	SUBMODULE EHXPLLJ
+		INSTANCE PLLInst_0
+	SUBMODULE VLO
+		INSTANCE scuba_vlo_inst
--- a/display/fpga/ip/pll0/pll0.lpc
+++ b/display/fpga/ip/pll0/pll0.lpc
@ -0,0 +1,87 @@
+[Device]
+Family=machxo2
+PartType=LCMXO2-1200HC
+PartName=LCMXO2-1200HC-5SG32C
+SpeedGrade=5
+Package=QFN32
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll0
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/24/2018
+Time=22:15:53
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+mode=Frequency
+CLKI=12
+CLKI_DIV=1
+BW=1.146
+VCO=480.000
+fb_mode=CLKOP
+CLKFB_DIV=8
+FRACN_ENABLE=0
+FRACN_DIV=0
+DynamicPhase=STATIC
+ClkEnable=0
+Standby=0
+Enable_sel=0
+PLLRst=0
+PLLMRst=0
+ClkOS2Rst=0
+ClkOS3Rst=0
+LockSig=1
+LockStk=0
+WBProt=0
+OPBypass=0
+OPUseDiv=0
+CLKOP_DIV=5
+FREQ_PIN_CLKOP=96
+OP_Tol=0.0
+CLKOP_AFREQ=96.000000
+CLKOP_PHASEADJ=0
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+EnCLKOS=0
+OSBypass=0
+OSUseDiv=0
+CLKOS_DIV=1
+FREQ_PIN_CLKOS=100
+OS_Tol=0.0
+CLKOS_AFREQ=
+CLKOS_PHASEADJ=0
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+EnCLKOS2=0
+OS2Bypass=0
+OS2UseDiv=0
+CLKOS2_DIV=1
+FREQ_PIN_CLKOS2=100
+OS2_Tol=0.0
+CLKOS2_AFREQ=
+CLKOS2_PHASEADJ=0
+EnCLKOS3=0
+OS3Bypass=0
+OS3UseDiv=0
+CLKOS3_DIV=1
+FREQ_PIN_CLKOS3=100
+OS3_Tol=0.0
+CLKOS3_AFREQ=
+CLKOS3_PHASEADJ=0
+
+[Command]
+cmd_line= -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock
--- a/display/fpga/ip/pll0/pll0.naf
+++ b/display/fpga/ip/pll0/pll0.naf
@ -0,0 +1,3 @@
+CLKI  i
+CLKOP  o
+LOCK  o
--- a/display/fpga/ip/pll0/pll0.sort
+++ b/display/fpga/ip/pll0/pll0.sort
@ -0,0 +1 @@
+pll0.vhd
--- a/display/fpga/ip/pll0/pll0.srp
+++ b/display/fpga/ip/pll0/pll0.srp
@ -0,0 +1,26 @@
+SCUBA, Version Diamond (64-bit) 3.10.0.111.2
+Tue Apr 24 22:15:53 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+    Issued command   : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock 
+    Circuit name     : pll0
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP, LOCK
+    I/O buffer       : not inserted
+    EDIF output      : pll0.edn
+    VHDL output      : pll0.vhd
+    VHDL template    : pll0_tmpl.vhd
+    VHDL purpose     : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll0.srp
+    Element Usage    :
+        EHXPLLJ : 1
+    Estimated Resource Usage:
--- a/display/fpga/ip/pll0/pll0.sym
+++ b/display/fpga/ip/pll0/pll0.sym
--- a/display/fpga/ip/pll0/pll0.vhd
+++ b/display/fpga/ip/pll0/pll0.vhd
@ -0,0 +1,154 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
+-- Module  Version: 5.7
+--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock 
+
+-- Tue Apr 24 22:15:53 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO2;
+use MACHXO2.components.all;
+-- synopsys translate_on
+
+entity pll0 is
+    port (
+        CLKI: in  std_logic; 
+        CLKOP: out  std_logic; 
+        LOCK: out  std_logic);
+end pll0;
+
+architecture Structure of pll0 is
+
+    -- internal signal declarations
+    signal CLKOP_t: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component EHXPLLJ
+        generic (INTFB_WAKE : in String; DDRST_ENA : in String; 
+                DCRST_ENA : in String; MRST_ENA : in String; 
+                PLLRST_ENA : in String; DPHASE_SOURCE : in String; 
+                STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String; 
+                OUTDIVIDER_MUXC2 : in String; 
+                OUTDIVIDER_MUXB2 : in String; 
+                OUTDIVIDER_MUXA2 : in String; 
+                PREDIVIDER_MUXD1 : in Integer; 
+                PREDIVIDER_MUXC1 : in Integer; 
+                PREDIVIDER_MUXB1 : in Integer; 
+                PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String; 
+                PLL_LOCK_MODE : in Integer; 
+                CLKOS_TRIM_DELAY : in Integer; 
+                CLKOS_TRIM_POL : in String; 
+                CLKOP_TRIM_DELAY : in Integer; 
+                CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer; 
+                FRACN_ENABLE : in String; FEEDBK_PATH : in String; 
+                CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer; 
+                CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer; 
+                CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer; 
+                CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer; 
+                VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String; 
+                VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String; 
+                CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String; 
+                CLKOS_ENABLE : in String; CLKOP_ENABLE : in String; 
+                CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer; 
+                CLKOS_DIV : in Integer; CLKOP_DIV : in Integer; 
+                CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
+        port (CLKI: in  std_logic; CLKFB: in  std_logic; 
+            PHASESEL1: in  std_logic; PHASESEL0: in  std_logic; 
+            PHASEDIR: in  std_logic; PHASESTEP: in  std_logic; 
+            LOADREG: in  std_logic; STDBY: in  std_logic; 
+            PLLWAKESYNC: in  std_logic; RST: in  std_logic; 
+            RESETM: in  std_logic; RESETC: in  std_logic; 
+            RESETD: in  std_logic; ENCLKOP: in  std_logic; 
+            ENCLKOS: in  std_logic; ENCLKOS2: in  std_logic; 
+            ENCLKOS3: in  std_logic; PLLCLK: in  std_logic; 
+            PLLRST: in  std_logic; PLLSTB: in  std_logic; 
+            PLLWE: in  std_logic; PLLADDR4: in  std_logic; 
+            PLLADDR3: in  std_logic; PLLADDR2: in  std_logic; 
+            PLLADDR1: in  std_logic; PLLADDR0: in  std_logic; 
+            PLLDATI7: in  std_logic; PLLDATI6: in  std_logic; 
+            PLLDATI5: in  std_logic; PLLDATI4: in  std_logic; 
+            PLLDATI3: in  std_logic; PLLDATI2: in  std_logic; 
+            PLLDATI1: in  std_logic; PLLDATI0: in  std_logic; 
+            CLKOP: out  std_logic; CLKOS: out  std_logic; 
+            CLKOS2: out  std_logic; CLKOS3: out  std_logic; 
+            LOCK: out  std_logic; INTLOCK: out  std_logic; 
+            REFCLK: out  std_logic; CLKINTFB: out  std_logic; 
+            DPHSRC: out  std_logic; PLLACK: out  std_logic; 
+            PLLDATO7: out  std_logic; PLLDATO6: out  std_logic; 
+            PLLDATO5: out  std_logic; PLLDATO4: out  std_logic; 
+            PLLDATO3: out  std_logic; PLLDATO2: out  std_logic; 
+            PLLDATO1: out  std_logic; PLLDATO0: out  std_logic);
+    end component;
+    attribute FREQUENCY_PIN_CLKOP : string; 
+    attribute FREQUENCY_PIN_CLKI : string; 
+    attribute ICP_CURRENT : string; 
+    attribute LPF_RESISTOR : string; 
+    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "96.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "12.000000";
+    attribute ICP_CURRENT of PLLInst_0 : label is "7";
+    attribute LPF_RESISTOR of PLLInst_0 : label is "8";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    PLLInst_0: EHXPLLJ
+        generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED", 
+        MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", 
+        STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", 
+        PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=>  0, CLKOS3_CPHASE=>  0, 
+        CLKOS2_FPHASE=>  0, CLKOS2_CPHASE=>  0, CLKOS_FPHASE=>  0, 
+        CLKOS_CPHASE=>  0, CLKOP_FPHASE=>  0, CLKOP_CPHASE=>  4, 
+        PLL_LOCK_MODE=>  0, CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "FALLING", 
+        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=>  0, 
+        FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD", 
+        PREDIVIDER_MUXD1=>  0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=>  0, VCO_BYPASS_C0=> "DISABLED", 
+        CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "DIVB", 
+        PREDIVIDER_MUXB1=>  0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "DISABLED", 
+        OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=>  0, VCO_BYPASS_A0=> "DISABLED", 
+        CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=>  1, CLKOS2_DIV=>  1, 
+        CLKOS_DIV=>  1, CLKOP_DIV=>  5, CLKFB_DIV=>  8, CLKI_DIV=>  1, 
+        FEEDBK_PATH=> "CLKOP")
+        port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, 
+            PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, 
+            PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo, 
+            PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo, 
+            RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo, 
+            ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo, 
+            PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo, 
+            PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo, 
+            PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo, 
+            PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo, 
+            PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo, 
+            PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo, 
+            PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo, 
+            PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, 
+            CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, 
+            REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open, 
+            PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open, 
+            PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open, 
+            PLLDATO1=>open, PLLDATO0=>open);
+
+    CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library MACHXO2;
+configuration Structure_CON of pll0 is
+    for Structure
+        for all:VLO use entity MACHXO2.VLO(V); end for;
+        for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- a/display/fpga/ip/pll0/pll0_generate.log
+++ b/display/fpga/ip/pll0/pll0_generate.log
@ -0,0 +1,44 @@
+Starting process: Module
+
+Starting process: 
+
+SCUBA, Version Diamond (64-bit) 3.10.0.111.2
+Tue Apr 24 22:15:53 2018
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.
+
+BEGIN SCUBA Module Synthesis
+
+    Issued command   : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock 
+    Circuit name     : pll0
+    Module type      : pll
+    Module Version   : 5.7
+    Ports            : 
+	Inputs       : CLKI
+	Outputs      : CLKOP, LOCK
+    I/O buffer       : not inserted
+    EDIF output      : pll0.edn
+    VHDL output      : pll0.vhd
+    VHDL template    : pll0_tmpl.vhd
+    VHDL purpose     : for synthesis and simulation
+    Bus notation     : big endian
+    Report output    : pll0.srp
+    Estimated Resource Usage:
+
+END   SCUBA Module Synthesis
+
+File: pll0.lpc created.
+
+
+End process: completed successfully.
+
+
+Total Warnings:  0
+
+Total Errors:  0
+
+
--- a/display/fpga/ip/pll0/pll0_tmpl.vhd
+++ b/display/fpga/ip/pll0/pll0_tmpl.vhd
@ -0,0 +1,13 @@
+-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
+-- Module  Version: 5.7
+-- Tue Apr 24 22:15:53 2018
+
+-- parameterized module component declaration
+component pll0
+    port (CLKI: in  std_logic; CLKOP: out  std_logic; 
+        LOCK: out  std_logic);
+end component;
+
+-- parameterized module component instance
+__ : pll0
+    port map (CLKI=>__, CLKOP=>__, LOCK=>__);
--- a/display/fpga/sim_ip/gram0.vhd
+++ b/display/fpga/sim_ip/gram0.vhd
@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library generics;
+use generics.all;
+
+entity gram0 is
+	port(
+		DataInA  : in  std_logic_vector(8 downto 0);
+		DataInB  : in  std_logic_vector(8 downto 0);
+		AddressA : in  std_logic_vector(12 downto 0);
+		AddressB : in  std_logic_vector(12 downto 0);
+		ClockA   : in  std_logic;
+		ClockB   : in  std_logic;
+		ClockEnA : in  std_logic;
+		ClockEnB : in  std_logic;
+		WrA      : in  std_logic;
+		WrB      : in  std_logic;
+		ResetA   : in  std_logic;
+		ResetB   : in  std_logic;
+		QA       : out std_logic_vector(8 downto 0);
+		QB       : out std_logic_vector(8 downto 0));
+end gram0;
+
+architecture RTL of gram0 is
+
+begin
+	ram_inst : entity generics.ram
+		generic map(
+			WIDTH => 9,
+			DEPTH  => 13
+		)
+		port map(
+			clk        => ClockA,
+			rst        => ResetA,
+			a_addr_in  => AddressA,
+			a_data_in  => DataInA,
+			a_data_out => QA,
+			a_we       => WrA,
+			b_addr_in  => AddressB,
+			b_data_out => QB
+		);
+	
+end architecture RTL;
--- a/display/fpga/sim_ip/pll0.vhd
+++ b/display/fpga/sim_ip/pll0.vhd
@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pll0 is
+	port(
+		CLKI  : in  std_logic;
+		CLKOP : out std_logic;
+		LOCK  : out std_logic);
+end entity pll0;
+
+architecture RTL of pll0 is
+
+begin
+	LOCK <= '1';
+	clock_driver : process
+		constant period : time := (1 sec / 96000000);
+	begin
+		CLKOP <= '0';
+		wait for period / 2;
+		CLKOP <= '1';
+		wait for period / 2;
+	end process clock_driver;
+end architecture RTL;
--- a/display/kernel-driver/.gitignore
+++ b/display/kernel-driver/.gitignore
@ -0,0 +1,6 @@
+*.o
+*.ko
+*.mod.c
+modules.order
+Module.symvers
+*.pro.user
--- a/display/kernel-driver/Makefile
+++ b/display/kernel-driver/Makefile
@ -0,0 +1,14 @@
+obj-m := lmg6202ulyt.o
+KDIR := ~/projects/arm-linux/current
+PWD := $(shell pwd)
+default: lmg6202ulyt.ko
+lmg6202ulyt.ko: lmg6202ulyt.c
+	$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
+
+deploy: lmg6202ulyt.ko
+	scp $< markus@opi:/home/markus/lmg6202ulyt/deploy
+
+clean:
+	rm -f ./*.o ./*.ko ./*.mod.c modules.order Module.symvers
+
+.phony: deploy clean
--- a/display/kernel-driver/lmg6202ulyt.c
+++ b/display/kernel-driver/lmg6202ulyt.c
@ -0,0 +1,364 @@
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/spi/spi.h>
+#include <linux/of_device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/fb.h>
+
+#define BPP 8 // 8
+#define PIX_THRESHOLD 0
+
+#define LMGE_GPIO 100
+#define LMGE_OTHER 99
+
+#define PALETTE_SIZE 256
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Markus Koch");
+MODULE_DESCRIPTION("lmg6202ulyt display driver");
+MODULE_VERSION("0.1");
+
+static char *testparam = "param";
+module_param(testparam, charp, S_IRUGO);
+MODULE_PARM_DESC(testparam, "A test parameter");
+
+static struct of_device_id lmg6202ulyt_dt_ids[] = {
+{ .compatible = "hitachi,lmg6202ulyt", },
+{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, lmg6202ulyt_dt_ids);
+
+static const struct fb_videomode default_mode = {
+	NULL, 30, 480, 128, /* name, refresh, xres, yres */
+	39300, /* pixclk */
+	0, 0, 0, 0, /* margin l, r, t, b */
+	0, 0, /* hsync_len, vsync_len */
+	0, FB_VMODE_NONINTERLACED /* vmode, flag */
+};
+
+struct lmg6202ulyt_priv {
+	struct spi_device *spi;
+	struct fb_info info;
+
+	dma_addr_t fb_phys;
+	void __iomem *fb_virt;
+	u32 pseudo_palette[PALETTE_SIZE];
+};
+
+static int lmg6202ulyt_init_var(struct lmg6202ulyt_priv *priv)
+{
+	struct fb_var_screeninfo *var = &priv->info.var;
+
+	var->accel_flags = FB_ACCEL_NONE;
+	var->activate = FB_ACTIVATE_NOW;
+	var->xres_virtual = var->xres;
+	var->yres_virtual = var->yres;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		var->red.offset = 0;
+		var->red.length = 8;
+		var->green.offset = 0;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		break;
+
+	case 16:
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		var->red.offset = 11;
+		var->red.length = 5;
+		var->green.offset = 5;
+		var->green.length = 6;
+		var->blue.offset = 0;
+		var->blue.length  = 5;
+		break;
+
+	case 24:
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		var->red.offset = 16;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		break;
+
+	case 32:
+		var->transp.offset = 24;
+		var->transp.length = 8;
+		var->red.offset = 16;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		break;
+	}
+
+	return 0;
+}
+
+static int lmg6202ulyt_init_fix(struct lmg6202ulyt_priv *priv)
+{
+	struct fb_var_screeninfo *var = &priv->info.var;
+	struct fb_fix_screeninfo *fix = &priv->info.fix;
+
+	strcpy(fix->id, "LW-35 LCD");
+
+	fix->line_length = var->xres * var->bits_per_pixel/8;
+	fix->smem_len = fix->line_length * var->yres;
+	fix->type = FB_TYPE_PACKED_PIXELS;
+
+	if (var->bits_per_pixel == 8 && !var->grayscale)
+		fix->visual = FB_VISUAL_PSEUDOCOLOR;
+	else
+		fix->visual = FB_VISUAL_TRUECOLOR;
+
+	printk(KERN_INFO "lmg6202ulyt: Using %d bpp.\n", var->bits_per_pixel);
+
+	return 0;
+}
+
+void lfb_mkdirty(struct fb_info *info, int y, int height)
+{
+	//struct lmg6202ulyt_priv *priv = info->par;
+	struct fb_deferred_io *fbdefio = info->fbdefio;
+
+	schedule_delayed_work(&info->deferred_work, fbdefio->delay);
+}
+
+static int lfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			 unsigned blue, unsigned transp,
+			 struct fb_info *info)
+{
+	//struct lmg6202ulyt_priv *fbdev = (struct lmg6202ulyt_priv *)info->par;
+	u32 color;
+
+	if (regno >= info->cmap.len) {
+		dev_err(info->device, "regno >= cmap.len\n");
+		return 1;
+	}
+
+	if (info->var.grayscale) {
+		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
+		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+	}
+
+	red >>= (16 - info->var.red.length);
+	green >>= (16 - info->var.green.length);
+	blue >>= (16 - info->var.blue.length);
+	transp >>= (16 - info->var.transp.length);
+
+	if (info->var.bits_per_pixel == 8 && !info->var.grayscale) {
+		regno <<= 2;
+		color = (red << 16) | (green << 8) | blue;
+		//ocfb_writereg(fbdev, OCFB_PALETTE + regno, color);
+	} else {
+		((u32 *)(info->pseudo_palette))[regno] =
+				(red << info->var.red.offset) |
+				(green << info->var.green.offset) |
+				(blue << info->var.blue.offset) |
+				(transp << info->var.transp.offset);
+	}
+
+	return 0;
+}
+
+void lfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
+{
+	sys_fillrect(info, rect);
+	lfb_mkdirty(info, rect->dy, rect->height);
+}
+
+void lfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
+{
+	sys_copyarea(info, area);
+	lfb_mkdirty(info, area->dy, area->height);
+}
+
+void lfb_imageblit(struct fb_info *info, const struct fb_image *image)
+{
+	sys_imageblit(info, image);
+	lfb_mkdirty(info, image->dy, image->height);
+}
+
+static struct fb_ops ocfb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_setcolreg	= lfb_setcolreg,
+	.fb_fillrect	= lfb_fillrect,
+	.fb_copyarea	= lfb_copyarea,
+	.fb_imageblit	= lfb_imageblit,
+};
+
+#define BLOCKMUL 4
+#define BLOCKSIZE 180 * BLOCKMUL /* 180 = 3 rows */
+#define ROWSPERBLOCK (3 * BLOCKMUL)
+#define BLOCKCNT (128 / ROWSPERBLOCK) + 1
+void lmg6202ulyt_deferred_io(struct fb_info *info, struct list_head *pagelist)
+{
+	struct lmg6202ulyt_priv *priv = info->par;
+	char buf[BLOCKSIZE + 3] = {0x00,0x00,0x00,0x00,0x00};
+	int i;
+	int blk;
+	char __iomem *pixel;
+	int txsz;
+
+	spi_write(priv->spi, buf, 5);
+
+	pixel = info->screen_base;
+	for (blk = 0; blk < BLOCKCNT; ++blk) {
+		memset(buf, 0, sizeof(buf));
+		buf[0] = 1;
+
+		for (i = 0; i < BLOCKSIZE * 8; i++) {
+			if (*pixel > PIX_THRESHOLD) {
+				buf[(i / 8) + 1] |= (1 << (7 - (i % 8)));
+			}
+			if (pixel >= info->screen_base + info->screen_size - ((info->var.bits_per_pixel) / 8))
+				break;
+			pixel+= (info->var.bits_per_pixel) / 8;
+		}
+
+		if (blk == BLOCKCNT - 1)
+			txsz = sizeof(buf)/sizeof(buf[0]);
+		else
+			txsz = sizeof(buf)/sizeof(buf[0]);
+
+		spi_write(priv->spi, buf, txsz);
+	}
+}
+
+static int lmg6202ulyt_probe(struct spi_device *spi)
+{
+	struct lmg6202ulyt_priv *priv = NULL;
+	struct fb_deferred_io *fbdefio = NULL;
+	int fbsize;
+	int ret;
+
+	printk(KERN_INFO "lmg6202ulyt: probe\n");
+
+	priv = devm_kzalloc(&spi->dev,
+			    sizeof(struct lmg6202ulyt_priv),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	spi_set_drvdata(spi, priv);
+
+	priv->spi = spi;
+
+	priv->info.fbops = &ocfb_ops;
+	priv->info.device = &spi->dev;
+	priv->info.par = priv;
+
+
+	printk(KERN_INFO "lmg6202ulyt: vmode\n");
+
+	if (!fb_find_mode(&priv->info.var, &priv->info, "",
+			  NULL, 0, &default_mode, BPP)) {
+		dev_err(&spi->dev, "No valid video modes found\n");
+		return -EINVAL;
+	}
+
+	printk(KERN_INFO "lmg6202ulyt: Step 1\n");
+	lmg6202ulyt_init_var(priv);
+	printk(KERN_INFO "lmg6202ulyt: Step 1.5\n");
+	lmg6202ulyt_init_fix(priv);
+
+	printk(KERN_INFO "lmg6202ulyt: Step 2\n");
+	/* Allocate framebuffer memory */
+	fbsize = priv->info.fix.smem_len;
+	dma_set_coherent_mask(&spi->dev, 0xFFFFFFFF);
+	priv->fb_virt = dma_alloc_coherent(&spi->dev, PAGE_ALIGN(fbsize),
+					   &priv->fb_phys, GFP_KERNEL);
+	if (!priv->fb_virt) {
+		dev_err(&spi->dev,
+			"Frame buffer memory allocation failed\n");
+		return -ENOMEM;
+	}
+
+	printk(KERN_INFO, "lmg6202ulyt: fbdefio init\n");
+	fbdefio = devm_kzalloc(&spi->dev, sizeof(struct fb_deferred_io),
+			       GFP_KERNEL);
+	if (!fbdefio) {
+		dev_err(&spi->dev,
+			"FB defio memory allocation failed\n");
+		return -ENOMEM;
+	}
+
+	priv->info.fbdefio = fbdefio;
+
+	fbdefio->delay = HZ/30;
+	fbdefio->deferred_io = lmg6202ulyt_deferred_io;
+	fb_deferred_io_init(&priv->info);
+
+	printk(KERN_INFO "lmg6202ulyt: Step 3\n");
+	priv->info.fix.smem_start = priv->fb_phys;
+	priv->info.screen_base = priv->fb_virt;
+	priv->info.screen_size = fbsize;
+	priv->info.pseudo_palette = priv->pseudo_palette;
+
+	// HW specific init goes here
+
+	/* Allocate color map */
+	ret = fb_alloc_cmap(&priv->info.cmap, PALETTE_SIZE, 0);
+	if (ret) {
+		dev_err(&spi->dev, "Color map allocation failed\n");
+		goto err_dma_free;
+	}
+	printk(KERN_INFO "lmg6202ulyt: Step 4\n");
+
+	/* Register framebuffer */
+	ret = register_framebuffer(&priv->info);
+	if (ret) {
+		dev_err(&spi->dev, "Framebuffer registration failed\n");
+		goto err_dealloc_cmap;
+
+	}
+	printk(KERN_INFO "lmg6202ulyt: Loaded driver\n");
+
+	priv->info.var.grayscale = 1;
+
+	lfb_mkdirty(&priv->info, 0, 0);
+
+	return 0;
+
+err_dealloc_cmap:
+	fb_dealloc_cmap(&priv->info.cmap);
+
+err_dma_free:
+	//	kzfree(priv->fb_mem);
+	dma_free_coherent(&spi->dev, PAGE_ALIGN(fbsize), priv->fb_virt,
+			  priv->fb_phys);
+
+	return ret;
+}
+
+static int lmg6202ulyt_remove(struct spi_device *spi)
+{
+	struct lmg6202ulyt_priv *priv = spi_get_drvdata(spi);
+
+	//unregister_framebuffer(&priv->info);
+	fb_dealloc_cmap(&priv->info.cmap);
+
+	return 0;
+}
+
+static struct spi_driver lmg6202ulyt_driver = {
+	.probe = lmg6202ulyt_probe,
+	.remove = lmg6202ulyt_remove,
+	.driver = {
+		.name = "lmg6202ulyt",
+		.owner = THIS_MODULE,
+		.of_match_table = lmg6202ulyt_dt_ids,
+	},
+};
+module_spi_driver(lmg6202ulyt_driver);
+
--- a/display/kernel-driver/lmg6202ulyt.pro
+++ b/display/kernel-driver/lmg6202ulyt.pro
@ -0,0 +1,9 @@
+TEMPLATE = app
+CONFIG += console
+CONFIG -= app_bundle
+CONFIG -= qt
+
+INCLUDEPATH += /home/markus/projects/arm-linux/current/include
+
+SOURCES += \
+        lmg6202ulyt.c
--- a/display/tools/.gitignore
+++ b/display/tools/.gitignore
@ -0,0 +1,3 @@
+*.raw
+*.mem
+*.png
--- a/display/tools/mkimage.py
+++ b/display/tools/mkimage.py
@ -0,0 +1,38 @@
+#!/usr/bin/env python
+# This script generates a memory initialization file for Lattice Diamond.
+
+import sys
+from PIL import Image
+
+im = Image.open(sys.argv[1]);
+pix = im.load()
+
+buf=[""] * 4
+block=0
+extra=""
+pixcnt=0
+
+foo=0
+for y in range(0, im.size[1]):
+	for x in range(0,im.size[0]):
+		foo=foo+1
+		if block == 4:
+			buf[pixcnt] = buf[pixcnt] + str(pix[x,y])
+			if pixcnt == 3:
+				for i in range(0,4):
+					print(buf[i])
+					buf[i] = ""
+				block = 0
+				pixcnt = 0
+			else:
+				pixcnt = pixcnt + 1
+		else:
+			buf[block] = buf[block] + str(pix[x,y])
+			if (pixcnt == 7):
+				block = block + 1
+				pixcnt = 0
+			else:
+				pixcnt = pixcnt + 1
+	
+	print("")
+
--- a/display/tools/mkraw.py
+++ b/display/tools/mkraw.py
@ -0,0 +1,20 @@
+#!/usr/bin/env python
+# This script generates a raw image file for use with the userspace display driver.
+
+import sys
+
+from PIL import Image
+im = Image.open(sys.argv[1]);
+pix = im.load()
+
+data=0
+
+foo=0
+for y in range(0, im.size[1]):
+	for x in range(0,im.size[0]):
+		if (pix[x,y]):
+			data = data | (1 << (7 - (x % 8)))
+		if (((x+1) % 8) == 0):
+			sys.stdout.buffer.write(data.to_bytes(1, byteorder='big'))
+			data = 0
+
--- a/display/userspace-driver/.gitignore
+++ b/display/userspace-driver/.gitignore
@ -0,0 +1,2 @@
+*.o
+main
--- a/display/userspace-driver/loop.sh
+++ b/display/userspace-driver/loop.sh
@ -0,0 +1,9 @@
+while [ 1 ]; do
+	#cat /dev/zero | tr '\0' \x55 | ./main
+	#./main < /dev/urandom
+	for file in ./*.raw; do
+		echo $file
+		./main < $file
+		sleep 1
+	done
+done
--- a/display/userspace-driver/main.c
+++ b/display/userspace-driver/main.c
@ -0,0 +1,176 @@
+#include <stdint.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <linux/types.h>
+#include <linux/spi/spidev.h>
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+static void pabort(const char *s)
+{
+	perror(s);
+	abort();
+}
+
+// LCM(bits) = 1440 to be even on a row boundary
+//           => Blocksize 180 bytes, 3 rows
+#define MINBLK 180
+#define BLKMUL 4
+#define PLSIZE (MINBLK*BLKMUL + 3)
+#define ROWSPERBLOCK (3 * BLKMUL)
+#define BLKCNT (128 / ROWSPERBLOCK) + 1
+
+int get_addr(int x, int y)
+{
+	int byteno;
+	byteno = (y * 480 + x) / 8;
+	if (x % 8 || byteno % 9) {
+		printf("ERROR: Invalid get_addr offset. Must be on 9 byte boundary.\n");
+		return -1;
+	}
+	byteno -= byteno / 9;
+	printf("addr = %d\n", byteno);
+	return byteno;
+}
+
+// Row must be multiple of 3
+static void transfer(int fd, uint8_t *memory)
+{
+	int ret;
+	uint8_t *tx;
+	//uint8_t *rx;
+	int i;
+	int txlen;
+	int addr;
+	int blk;
+	
+	txlen = PLSIZE;
+	
+	//tx = malloc(txlen * sizeof(uint8_t));
+	//rx = malloc(PLSIZE * sizeof(uint8_t));
+	tx = memory;
+
+	
+	struct spi_ioc_transfer tr = {
+		.tx_buf = (unsigned long)tx,
+		.rx_buf = (unsigned long)NULL,
+		.len = txlen,
+		.delay_usecs = 10,
+		.speed_hz = 0,
+		.bits_per_word = 0,
+	};
+
+	for (blk = 0; blk < BLKCNT; ++blk) {
+		printf("tx = %d\n", tx - memory);
+		addr = get_addr(0, blk * ROWSPERBLOCK);
+		
+		tx[0] = 0x00; // Opcode: 0
+		tx[1] = (addr >> 8) & 0xFF; // Base addr: 
+		tx[2] = addr & 0xFF;
+	
+		tr.tx_buf = (unsigned long)tx; // TODO
+		tr.len = txlen;
+		
+		ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+		if (ret == 1)
+			pabort("can't send spi message");
+		
+		tx += ROWSPERBLOCK * (480/8);
+	}
+	
+	/*
+	for (ret = 0; ret < PLSIZE; ret++) {
+		if (!(ret % 6))
+			puts("");
+		printf("%.2X ", rx[ret]);
+	}
+	puts("");
+	*/
+	
+	//free(tx);
+	//free(rx);
+}
+
+int main(int argc, char *argv[])
+{
+	int fd;
+	int ret;
+	int i;
+	char temp;
+	
+	static uint8_t mode = 0;
+	static uint8_t bits = 8;
+	static uint32_t speed = 2000000;
+	
+	uint8_t memory[480*128/8 + 3];
+	uint8_t *image = memory + 3;
+	
+	for (i = 0; i < 0; i++) {
+		printf("%3d: %d\n", i, get_addr(i, 0));
+		if ((i+1)%8 == 0) {
+			printf("\n");
+		}
+	}
+	
+	fd = open("/dev/spidev0.0", O_RDWR);
+	if (fd < 0)
+		pabort("can't open device");
+	
+	/*
+	 * spi mode
+	 */
+	ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
+	if (ret == -1)
+		pabort("can't set spi mode");
+
+	ret = ioctl(fd, SPI_IOC_RD_MODE, &mode);
+	if (ret == -1)
+		pabort("can't get spi mode");
+
+	/*
+	 * bits per word
+	 */
+	ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+	if (ret == -1)
+		pabort("can't set bits per word");
+
+	ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
+	if (ret == -1)
+		pabort("can't get bits per word");
+
+	/*
+	 * max speed hz
+	 */
+	ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+	if (ret == -1)
+		pabort("can't set max speed hz");
+
+	ret = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed);
+	if (ret == -1)
+		pabort("can't get max speed hz");
+
+	//printf("spi mode: %d\n", mode);
+	//printf("bits per word: %d\n", bits);
+	//printf("max speed: %d Hz (%d KHz)\n", speed, speed/1000);
+
+	for (i = 3; i < ARRAY_SIZE(memory); i++) {
+		memory[i] = i*8/480;
+		fread(&temp, 1,1, stdin);
+		if (i < 720+3)
+			memory[i] = 0xAA;
+		else if (i < 720*2+3)
+			memory[i] = 0xFF;
+		else
+			memory[i] = 0x55;
+		memory[i] = temp;
+		//rx[i] = 0;
+	}
+		
+	transfer(fd, memory);
+	
+	close(fd);
+}