lw35-upgrade/display/fpga/ip/pll0/pll0_tmpl.vhd

14 lines
393 B
VHDL

-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.7
-- Tue Apr 24 22:15:53 2018
-- parameterized module component declaration
component pll0
port (CLKI: in std_logic; CLKOP: out std_logic;
LOCK: out std_logic);
end component;
-- parameterized module component instance
__ : pll0
port map (CLKI=>__, CLKOP=>__, LOCK=>__);