155 lines
7.5 KiB
VHDL
155 lines
7.5 KiB
VHDL
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-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
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-- Module Version: 5.7
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--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock
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-- Tue Apr 24 22:15:53 2018
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library IEEE;
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use IEEE.std_logic_1164.all;
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-- synopsys translate_off
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library MACHXO2;
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use MACHXO2.components.all;
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-- synopsys translate_on
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entity pll0 is
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port (
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CLKI: in std_logic;
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CLKOP: out std_logic;
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LOCK: out std_logic);
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end pll0;
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architecture Structure of pll0 is
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-- internal signal declarations
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signal CLKOP_t: std_logic;
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signal scuba_vlo: std_logic;
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-- local component declarations
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component VLO
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port (Z: out std_logic);
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end component;
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component EHXPLLJ
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generic (INTFB_WAKE : in String; DDRST_ENA : in String;
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DCRST_ENA : in String; MRST_ENA : in String;
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PLLRST_ENA : in String; DPHASE_SOURCE : in String;
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STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
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OUTDIVIDER_MUXC2 : in String;
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OUTDIVIDER_MUXB2 : in String;
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OUTDIVIDER_MUXA2 : in String;
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PREDIVIDER_MUXD1 : in Integer;
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PREDIVIDER_MUXC1 : in Integer;
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PREDIVIDER_MUXB1 : in Integer;
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PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
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PLL_LOCK_MODE : in Integer;
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CLKOS_TRIM_DELAY : in Integer;
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CLKOS_TRIM_POL : in String;
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CLKOP_TRIM_DELAY : in Integer;
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CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
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FRACN_ENABLE : in String; FEEDBK_PATH : in String;
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CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
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CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
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CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
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CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
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VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
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VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
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CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
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CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
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CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
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CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
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CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
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port (CLKI: in std_logic; CLKFB: in std_logic;
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PHASESEL1: in std_logic; PHASESEL0: in std_logic;
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PHASEDIR: in std_logic; PHASESTEP: in std_logic;
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LOADREG: in std_logic; STDBY: in std_logic;
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PLLWAKESYNC: in std_logic; RST: in std_logic;
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RESETM: in std_logic; RESETC: in std_logic;
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RESETD: in std_logic; ENCLKOP: in std_logic;
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ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
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ENCLKOS3: in std_logic; PLLCLK: in std_logic;
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PLLRST: in std_logic; PLLSTB: in std_logic;
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PLLWE: in std_logic; PLLADDR4: in std_logic;
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PLLADDR3: in std_logic; PLLADDR2: in std_logic;
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PLLADDR1: in std_logic; PLLADDR0: in std_logic;
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PLLDATI7: in std_logic; PLLDATI6: in std_logic;
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PLLDATI5: in std_logic; PLLDATI4: in std_logic;
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PLLDATI3: in std_logic; PLLDATI2: in std_logic;
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PLLDATI1: in std_logic; PLLDATI0: in std_logic;
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CLKOP: out std_logic; CLKOS: out std_logic;
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CLKOS2: out std_logic; CLKOS3: out std_logic;
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LOCK: out std_logic; INTLOCK: out std_logic;
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REFCLK: out std_logic; CLKINTFB: out std_logic;
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DPHSRC: out std_logic; PLLACK: out std_logic;
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PLLDATO7: out std_logic; PLLDATO6: out std_logic;
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PLLDATO5: out std_logic; PLLDATO4: out std_logic;
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PLLDATO3: out std_logic; PLLDATO2: out std_logic;
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PLLDATO1: out std_logic; PLLDATO0: out std_logic);
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end component;
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attribute FREQUENCY_PIN_CLKOP : string;
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attribute FREQUENCY_PIN_CLKI : string;
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attribute ICP_CURRENT : string;
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attribute LPF_RESISTOR : string;
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attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "96.000000";
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attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "12.000000";
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attribute ICP_CURRENT of PLLInst_0 : label is "7";
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attribute LPF_RESISTOR of PLLInst_0 : label is "8";
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attribute syn_keep : boolean;
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attribute NGD_DRC_MASK : integer;
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attribute NGD_DRC_MASK of Structure : architecture is 1;
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begin
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-- component instantiation statements
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scuba_vlo_inst: VLO
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port map (Z=>scuba_vlo);
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PLLInst_0: EHXPLLJ
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generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
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MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
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STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
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PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0,
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CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0,
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CLKOS_CPHASE=> 0, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 4,
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PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
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CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0,
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FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
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PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
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CLKOS2_ENABLE=> "DISABLED", OUTDIVIDER_MUXB2=> "DIVB",
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PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "DISABLED",
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OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
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CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, CLKOS2_DIV=> 1,
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CLKOS_DIV=> 1, CLKOP_DIV=> 5, CLKFB_DIV=> 8, CLKI_DIV=> 1,
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FEEDBK_PATH=> "CLKOP")
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port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
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PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
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PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
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PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
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RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
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ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
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PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
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PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
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PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
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PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
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PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
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PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
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PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
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PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open,
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CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
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REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open,
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PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
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PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
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PLLDATO1=>open, PLLDATO0=>open);
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CLKOP <= CLKOP_t;
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end Structure;
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-- synopsys translate_off
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library MACHXO2;
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configuration Structure_CON of pll0 is
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for Structure
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for all:VLO use entity MACHXO2.VLO(V); end for;
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for all:EHXPLLJ use entity MACHXO2.EHXPLLJ(V); end for;
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end for;
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end Structure_CON;
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-- synopsys translate_on
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