lw35-upgrade/display/fpga/ip/gram0/gram0.lpc

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2018-04-30 09:08:47 +02:00
[Device]
Family=machxo2
PartType=LCMXO2-1200HC
PartName=LCMXO2-1200HC-5SG32C
SpeedGrade=5
Package=QFN32
OperatingCondition=COM
Status=S
[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=RAM_DP_TRUE
CoreRevision=7.5
ModuleName=gram0
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=04/22/2018
Time=17:34:06
[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
RAddress=7000
RData=9
WAddress=7000
WData=9
ROutputEn=1
RClockEn=0
WOutputEn=1
WClockEn=0
enByte=0
ByteSize=8
Optimization=Speed
Reset=Sync
Reset1=Sync
Init=mem
MemFile=/home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem
MemFormat=bin
EnECC=0
Pipeline=0
WriteA=Normal
WriteB=Normal
init_data=0
[FilesGenerated]
/home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem=mem
[Command]
cmd_line= -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-1200HC -aaddr_width 13 -widtha 9 -baddr_width 13 -widthb 9 -anum_words 7000 -bnum_words 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/workspaceSigasi/lmg6202/bin/gram_init.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL