lw35-upgrade/display/fpga/sim_ip/pll0.vhd

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VHDL
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2018-04-30 09:08:47 +02:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pll0 is
port(
CLKI : in std_logic;
CLKOP : out std_logic;
LOCK : out std_logic);
end entity pll0;
architecture RTL of pll0 is
begin
LOCK <= '1';
clock_driver : process
constant period : time := (1 sec / 96000000);
begin
CLKOP <= '0';
wait for period / 2;
CLKOP <= '1';
wait for period / 2;
end process clock_driver;
end architecture RTL;